trafic.map.qmsg

fpga交通控制灯

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 14 19:41:45 2008 " "Info: Processing started: Fri Nov 14 19:41:45 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off trafic -c trafic " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off trafic -c trafic" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../fenwei/fenwei.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../fenwei/fenwei.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fenwei-beha " "Info: Found design unit 1: fenwei-beha" {  } { { "../fenwei/fenwei.vhd" "" { Text "D:/VHDL/trafic/fenwei/fenwei.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fenwei " "Info: Found entity 1: fenwei" {  } { { "../fenwei/fenwei.vhd" "" { Text "D:/VHDL/trafic/fenwei/fenwei.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../fenpin/frequency1hz/frequency1hz.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../fenpin/frequency1hz/frequency1hz.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 frequency1hz-beha " "Info: Found design unit 1: frequency1hz-beha" {  } { { "../fenpin/frequency1hz/frequency1hz.vhd" "" { Text "D:/VHDL/trafic/fenpin/frequency1hz/frequency1hz.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 frequency1hz " "Info: Found entity 1: frequency1hz" {  } { { "../fenpin/frequency1hz/frequency1hz.vhd" "" { Text "D:/VHDL/trafic/fenpin/frequency1hz/frequency1hz.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../fenpin/frequency1khz/frequence1khz.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../fenpin/frequency1khz/frequence1khz.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 frequence1khz-beha " "Info: Found design unit 1: frequence1khz-beha" {  } { { "../fenpin/frequency1khz/frequence1khz.vhd" "" { Text "D:/VHDL/trafic/fenpin/frequency1khz/frequence1khz.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 frequence1khz " "Info: Found entity 1: frequence1khz" {  } { { "../fenpin/frequency1khz/frequence1khz.vhd" "" { Text "D:/VHDL/trafic/fenpin/frequency1khz/frequence1khz.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../display/display.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../display/display.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 display-beha " "Info: Found design unit 1: display-beha" {  } { { "../display/display.vhd" "" { Text "D:/VHDL/trafic/display/display.vhd" 22 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 display " "Info: Found entity 1: display" {  } { { "../display/display.vhd" "" { Text "D:/VHDL/trafic/display/display.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../display/comp_decoder/decoder.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../display/comp_decoder/decoder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 decoder-beha " "Info: Found design unit 1: decoder-beha" {  } { { "../display/comp_decoder/decoder.vhd" "" { Text "D:/VHDL/trafic/display/comp_decoder/decoder.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 decoder " "Info: Found entity 1: decoder" {  } { { "../display/comp_decoder/decoder.vhd" "" { Text "D:/VHDL/trafic/display/comp_decoder/decoder.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../center/center.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../center/center.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 center-beha " "Info: Found design unit 1: center-beha" {  } { { "../center/center.vhd" "" { Text "D:/VHDL/trafic/center/center.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 center " "Info: Found entity 1: center" {  } { { "../center/center.vhd" "" { Text "D:/VHDL/trafic/center/center.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../fenwei/trafic.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../fenwei/trafic.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 trafic " "Info: Found entity 1: trafic" {  } { { "../fenwei/trafic.bdf" "" { Schematic "D:/VHDL/trafic/fenwei/trafic.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "trafic " "Info: Elaborating entity \"trafic\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "center center:inst " "Info: Elaborating entity \"center\" for hierarchy \"center:inst\"" {  } { { "../fenwei/trafic.bdf" "inst" { Schematic "D:/VHDL/trafic/fenwei/trafic.bdf" { { 24 344 472 216 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "frequency1hz frequency1hz:inst4 " "Info: Elaborating entity \"frequency1hz\" for hierarchy \"frequency1hz:inst4\"" {  } { { "../fenwei/trafic.bdf" "inst4" { Schematic "D:/VHDL/trafic/fenwei/trafic.bdf" { { 24 96 192 120 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "frequence1khz frequence1khz:inst3 " "Info: Elaborating entity \"frequence1khz\" for hierarchy \"frequence1khz:inst3\"" {  } { { "../fenwei/trafic.bdf" "inst3" { Schematic "D:/VHDL/trafic/fenwei/trafic.bdf" { { 24 -40 56 120 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "display display:inst1 " "Info: Elaborating entity \"display\" for hierarchy \"display:inst1\"" {  } { { "../fenwei/trafic.bdf" "inst1" { Schematic "D:/VHDL/trafic/fenwei/trafic.bdf" { { 256 336 496 608 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "z display.vhd(132) " "Warning (10492): VHDL Process Statement warning at display.vhd(132): signal \"z\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../display/display.vhd" "" { Text "D:/VHDL/trafic/display/display.vhd" 132 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "display_v display.vhd(135) " "Warning (10492): VHDL Process Statement warning at display.vhd(135): signal \"display_v\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../display/display.vhd" "" { Text "D:/VHDL/trafic/display/display.vhd" 135 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "display_v display.vhd(138) " "Warning (10492): VHDL Process Statement warning at display.vhd(138): signal \"display_v\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../display/display.vhd" "" { Text "D:/VHDL/trafic/display/display.vhd" 138 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decoder display:inst1\|decoder:U1 " "Info: Elaborating entity \"decoder\" for hierarchy \"display:inst1\|decoder:U1\"" {  } { { "../display/display.vhd" "U1" { Text "D:/VHDL/trafic/display/display.vhd" 34 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fenwei fenwei:inst2 " "Info: Elaborating entity \"fenwei\" for hierarchy \"fenwei:inst2\"" {  } { { "../fenwei/trafic.bdf" "inst2" { Schematic "D:/VHDL/trafic/fenwei/trafic.bdf" { { 416 -32 144 512 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "fenwei:inst5\|num_shi\[2\] data_in GND " "Warning: Reduced register \"fenwei:inst5\|num_shi\[2\]\" with stuck data_in port to stuck value GND" {  } { { "../fenwei/fenwei.vhd" "" { Text "D:/VHDL/trafic/fenwei/fenwei.vhd" 16 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "fenwei:inst5\|num_shi\[3\] data_in GND " "Warning: Reduced register \"fenwei:inst5\|num_shi\[3\]\" with stuck data_in port to stuck value GND" {  } { { "../fenwei/fenwei.vhd" "" { Text "D:/VHDL/trafic/fenwei/fenwei.vhd" 16 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "fenwei:inst2\|num_shi\[2\] data_in GND " "Warning: Reduced register \"fenwei:inst2\|num_shi\[2\]\" with stuck data_in port to stuck value GND" {  } { { "../fenwei/fenwei.vhd" "" { Text "D:/VHDL/trafic/fenwei/fenwei.vhd" 16 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "fenwei:inst2\|num_shi\[3\] data_in GND " "Warning: Reduced register \"fenwei:inst2\|num_shi\[3\]\" with stuck data_in port to stuck value GND" {  } { { "../fenwei/fenwei.vhd" "" { Text "D:/VHDL/trafic/fenwei/fenwei.vhd" 16 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "display:inst1\|count1\[0\] display:inst1\|count\[0\] " "Info: Duplicate register \"display:inst1\|count1\[0\]\" merged to single register \"display:inst1\|count\[0\]\"" {  } { { "../display/display.vhd" "" { Text "D:/VHDL/trafic/display/display.vhd" 123 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "frequency1hz:inst4\|count\[0\] display:inst1\|count\[0\] " "Info: Duplicate register \"frequency1hz:inst4\|count\[0\]\" merged to single register \"display:inst1\|count\[0\]\"" {  } { { "../fenpin/frequency1hz/frequency1hz.vhd" "" { Text "D:/VHDL/trafic/fenpin/frequency1hz/frequency1hz.vhd" 16 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "frequency1hz:inst4\|count\[1\] display:inst1\|count\[1\] " "Info: Duplicate register \"frequency1hz:inst4\|count\[1\]\" merged to single register \"display:inst1\|count\[1\]\"" {  } { { "../fenpin/frequency1hz/frequency1hz.vhd" "" { Text "D:/VHDL/trafic/fenpin/frequency1hz/frequency1hz.vhd" 16 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "display:inst1\|count1\[1\] display:inst1\|count\[1\] " "Info: Duplicate register \"display:inst1\|count1\[1\]\" merged to single register \"display:inst1\|count\[1\]\"" {  } { { "../display/display.vhd" "" { Text "D:/VHDL/trafic/display/display.vhd" 123 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "181 " "Info: Implemented 181 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "162 " "Info: Implemented 162 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 7 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "142 " "Info: Allocated 142 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 14 19:41:50 2008 " "Info: Processing ended: Fri Nov 14 19:41:50 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}