trafic.tan.qmsg

fpga交通控制灯

{ "Info" "ITDB_TH_RESULT" "center:inst\|count\[0\] hold clk 3.689 ns register " "Info: th for register \"center:inst\|count\[0\]\" (data pin = \"hold\", clock pin = \"clk\") is 3.689 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.569 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 12.569 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_J4 22 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 22; CLK Node = 'clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../fenwei/trafic.bdf" "" { Schematic "D:/VHDL/trafic/fenwei/trafic.bdf" { { 48 -376 -208 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns frequence1khz:inst3\|z 2 REG LC_X8_Y13_N2 20 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N2; Fanout = 20; REG Node = 'frequence1khz:inst3\|z'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.966 ns" { clk frequence1khz:inst3|z } "NODE_NAME" } } { "../fenpin/frequency1khz/frequence1khz.vhd" "" { Text "D:/VHDL/trafic/fenpin/frequency1khz/frequence1khz.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.619 ns) + CELL(0.935 ns) 7.989 ns frequency1hz:inst4\|z 3 REG LC_X9_Y13_N5 24 " "Info: 3: + IC(3.619 ns) + CELL(0.935 ns) = 7.989 ns; Loc. = LC_X9_Y13_N5; Fanout = 24; REG Node = 'frequency1hz:inst4\|z'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.554 ns" { frequence1khz:inst3|z frequency1hz:inst4|z } "NODE_NAME" } } { "../fenpin/frequency1hz/frequency1hz.vhd" "" { Text "D:/VHDL/trafic/fenpin/frequency1hz/frequency1hz.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.869 ns) + CELL(0.711 ns) 12.569 ns center:inst\|count\[0\] 4 REG LC_X32_Y11_N1 16 " "Info: 4: + IC(3.869 ns) + CELL(0.711 ns) = 12.569 ns; Loc. = LC_X32_Y11_N1; Fanout = 16; REG Node = 'center:inst\|count\[0\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.580 ns" { frequency1hz:inst4|z center:inst|count[0] } "NODE_NAME" } } { "../center/center.vhd" "" { Text "D:/VHDL/trafic/center/center.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 32.22 % ) " "Info: Total cell delay = 4.050 ns ( 32.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.519 ns ( 67.78 % ) " "Info: Total interconnect delay = 8.519 ns ( 67.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "12.569 ns" { clk frequence1khz:inst3|z frequency1hz:inst4|z center:inst|count[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "12.569 ns" { clk clk~out0 frequence1khz:inst3|z frequency1hz:inst4|z center:inst|count[0] } { 0.000ns 0.000ns 1.031ns 3.619ns 3.869ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "../center/center.vhd" "" { Text "D:/VHDL/trafic/center/center.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.895 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.895 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns hold 1 PIN PIN_A12 20 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_A12; Fanout = 20; PIN Node = 'hold'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { hold } "NODE_NAME" } } { "../fenwei/trafic.bdf" "" { Schematic "D:/VHDL/trafic/fenwei/trafic.bdf" { { 136 -376 -208 152 "hold" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.813 ns) + CELL(0.607 ns) 8.895 ns center:inst\|count\[0\] 2 REG LC_X32_Y11_N1 16 " "Info: 2: + IC(6.813 ns) + CELL(0.607 ns) = 8.895 ns; Loc. = LC_X32_Y11_N1; Fanout = 16; REG Node = 'center:inst\|count\[0\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.420 ns" { hold center:inst|count[0] } "NODE_NAME" } } { "../center/center.vhd" "" { Text "D:/VHDL/trafic/center/center.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.082 ns ( 23.41 % ) " "Info: Total cell delay = 2.082 ns ( 23.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.813 ns ( 76.59 % ) " "Info: Total interconnect delay = 6.813 ns ( 76.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.895 ns" { hold center:inst|count[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.895 ns" { hold hold~out0 center:inst|count[0] } { 0.000ns 0.000ns 6.813ns } { 0.000ns 1.475ns 0.607ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "12.569 ns" { clk frequence1khz:inst3|z frequency1hz:inst4|z center:inst|count[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "12.569 ns" { clk clk~out0 frequence1khz:inst3|z frequency1hz:inst4|z center:inst|count[0] } { 0.000ns 0.000ns 1.031ns 3.619ns 3.869ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.895 ns" { hold center:inst|count[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.895 ns" { hold hold~out0 center:inst|count[0] } { 0.000ns 0.000ns 6.813ns } { 0.000ns 1.475ns 0.607ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "101 " "Info: Allocated 101 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 14 19:42:16 2008 " "Info: Processing ended: Fri Nov 14 19:42:16 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}