trafic.tan.qmsg

fpga交通控制灯

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "frequence1khz:inst3\|z " "Info: Detected ripple clock \"frequence1khz:inst3\|z\" as buffer" {  } { { "../fenpin/frequency1khz/frequence1khz.vhd" "" { Text "D:/VHDL/trafic/fenpin/frequency1khz/frequence1khz.vhd" 16 -1 0 } } { "c:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "frequence1khz:inst3\|z" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "frequency1hz:inst4\|z " "Info: Detected ripple clock \"frequency1hz:inst4\|z\" as buffer" {  } { { "../fenpin/frequency1hz/frequency1hz.vhd" "" { Text "D:/VHDL/trafic/fenpin/frequency1hz/frequency1hz.vhd" 16 -1 0 } } { "c:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "frequency1hz:inst4\|z" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register center:inst\|numb\[1\] register fenwei:inst2\|num_ge\[1\] 89.1 MHz 11.223 ns Internal " "Info: Clock \"clk\" has Internal fmax of 89.1 MHz between source register \"center:inst\|numb\[1\]\" and destination register \"fenwei:inst2\|num_ge\[1\]\" (period= 11.223 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.504 ns + Longest register register " "Info: + Longest register to register delay is 1.504 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns center:inst\|numb\[1\] 1 REG LC_X31_Y10_N0 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y10_N0; Fanout = 4; REG Node = 'center:inst\|numb\[1\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { center:inst|numb[1] } "NODE_NAME" } } { "../center/center.vhd" "" { Text "D:/VHDL/trafic/center/center.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.766 ns) + CELL(0.738 ns) 1.504 ns fenwei:inst2\|num_ge\[1\] 2 REG LC_X31_Y10_N2 7 " "Info: 2: + IC(0.766 ns) + CELL(0.738 ns) = 1.504 ns; Loc. = LC_X31_Y10_N2; Fanout = 7; REG Node = 'fenwei:inst2\|num_ge\[1\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.504 ns" { center:inst|numb[1] fenwei:inst2|num_ge[1] } "NODE_NAME" } } { "../fenwei/fenwei.vhd" "" { Text "D:/VHDL/trafic/fenwei/fenwei.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns ( 49.07 % ) " "Info: Total cell delay = 0.738 ns ( 49.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.766 ns ( 50.93 % ) " "Info: Total interconnect delay = 0.766 ns ( 50.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.504 ns" { center:inst|numb[1] fenwei:inst2|num_ge[1] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "1.504 ns" { center:inst|numb[1] fenwei:inst2|num_ge[1] } { 0.000ns 0.766ns } { 0.000ns 0.738ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-9.458 ns - Smallest " "Info: - Smallest clock skew is -9.458 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.111 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.111 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_J4 22 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 22; CLK Node = 'clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../fenwei/trafic.bdf" "" { Schematic "D:/VHDL/trafic/fenwei/trafic.bdf" { { 48 -376 -208 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.931 ns) + CELL(0.711 ns) 3.111 ns fenwei:inst2\|num_ge\[1\] 2 REG LC_X31_Y10_N2 7 " "Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X31_Y10_N2; Fanout = 7; REG Node = 'fenwei:inst2\|num_ge\[1\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.642 ns" { clk fenwei:inst2|num_ge[1] } "NODE_NAME" } } { "../fenwei/fenwei.vhd" "" { Text "D:/VHDL/trafic/fenwei/fenwei.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 70.07 % ) " "Info: Total cell delay = 2.180 ns ( 70.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.931 ns ( 29.93 % ) " "Info: Total interconnect delay = 0.931 ns ( 29.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.111 ns" { clk fenwei:inst2|num_ge[1] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.111 ns" { clk clk~out0 fenwei:inst2|num_ge[1] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.569 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 12.569 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_J4 22 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 22; CLK Node = 'clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../fenwei/trafic.bdf" "" { Schematic "D:/VHDL/trafic/fenwei/trafic.bdf" { { 48 -376 -208 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns frequence1khz:inst3\|z 2 REG LC_X8_Y13_N2 20 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N2; Fanout = 20; REG Node = 'frequence1khz:inst3\|z'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.966 ns" { clk frequence1khz:inst3|z } "NODE_NAME" } } { "../fenpin/frequency1khz/frequence1khz.vhd" "" { Text "D:/VHDL/trafic/fenpin/frequency1khz/frequence1khz.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.619 ns) + CELL(0.935 ns) 7.989 ns frequency1hz:inst4\|z 3 REG LC_X9_Y13_N5 24 " "Info: 3: + IC(3.619 ns) + CELL(0.935 ns) = 7.989 ns; Loc. = LC_X9_Y13_N5; Fanout = 24; REG Node = 'frequency1hz:inst4\|z'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.554 ns" { frequence1khz:inst3|z frequency1hz:inst4|z } "NODE_NAME" } } { "../fenpin/frequency1hz/frequency1hz.vhd" "" { Text "D:/VHDL/trafic/fenpin/frequency1hz/frequency1hz.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.869 ns) + CELL(0.711 ns) 12.569 ns center:inst\|numb\[1\] 4 REG LC_X31_Y10_N0 4 " "Info: 4: + IC(3.869 ns) + CELL(0.711 ns) = 12.569 ns; Loc. = LC_X31_Y10_N0; Fanout = 4; REG Node = 'center:inst\|numb\[1\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.580 ns" { frequency1hz:inst4|z center:inst|numb[1] } "NODE_NAME" } } { "../center/center.vhd" "" { Text "D:/VHDL/trafic/center/center.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 32.22 % ) " "Info: Total cell delay = 4.050 ns ( 32.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.519 ns ( 67.78 % ) " "Info: Total interconnect delay = 8.519 ns ( 67.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "12.569 ns" { clk frequence1khz:inst3|z frequency1hz:inst4|z center:inst|numb[1] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "12.569 ns" { clk clk~out0 frequence1khz:inst3|z frequency1hz:inst4|z center:inst|numb[1] } { 0.000ns 0.000ns 1.031ns 3.619ns 3.869ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.111 ns" { clk fenwei:inst2|num_ge[1] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.111 ns" { clk clk~out0 fenwei:inst2|num_ge[1] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "12.569 ns" { clk frequence1khz:inst3|z frequency1hz:inst4|z center:inst|numb[1] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "12.569 ns" { clk clk~out0 frequence1khz:inst3|z frequency1hz:inst4|z center:inst|numb[1] } { 0.000ns 0.000ns 1.031ns 3.619ns 3.869ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "../center/center.vhd" "" { Text "D:/VHDL/trafic/center/center.vhd" 35 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "../fenwei/fenwei.vhd" "" { Text "D:/VHDL/trafic/fenwei/fenwei.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.504 ns" { center:inst|numb[1] fenwei:inst2|num_ge[1] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "1.504 ns" { center:inst|numb[1] fenwei:inst2|num_ge[1] } { 0.000ns 0.766ns } { 0.000ns 0.738ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.111 ns" { clk fenwei:inst2|num_ge[1] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.111 ns" { clk clk~out0 fenwei:inst2|num_ge[1] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "12.569 ns" { clk frequence1khz:inst3|z frequency1hz:inst4|z center:inst|numb[1] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "12.569 ns" { clk clk~out0 frequence1khz:inst3|z frequency1hz:inst4|z center:inst|numb[1] } { 0.000ns 0.000ns 1.031ns 3.619ns 3.869ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "center:inst\|count\[4\] reset clk -2.554 ns register " "Info: tsu for register \"center:inst\|count\[4\]\" (data pin = \"reset\", clock pin = \"clk\") is -2.554 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.978 ns + Longest pin register " "Info: + Longest pin to register delay is 9.978 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns reset 1 PIN PIN_B12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_B12; Fanout = 1; PIN Node = 'reset'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "../fenwei/trafic.bdf" "" { Schematic "D:/VHDL/trafic/fenwei/trafic.bdf" { { 120 -376 -208 136 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.777 ns) + CELL(0.114 ns) 8.366 ns center:inst\|process0~0 2 COMB LC_X32_Y11_N0 6 " "Info: 2: + IC(6.777 ns) + CELL(0.114 ns) = 8.366 ns; Loc. = LC_X32_Y11_N0; Fanout = 6; COMB Node = 'center:inst\|process0~0'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.891 ns" { reset center:inst|process0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(1.112 ns) 9.978 ns center:inst\|count\[4\] 3 REG LC_X32_Y11_N5 12 " "Info: 3: + IC(0.500 ns) + CELL(1.112 ns) = 9.978 ns; Loc. = LC_X32_Y11_N5; Fanout = 12; REG Node = 'center:inst\|count\[4\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.612 ns" { center:inst|process0~0 center:inst|count[4] } "NODE_NAME" } } { "../center/center.vhd" "" { Text "D:/VHDL/trafic/center/center.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.701 ns ( 27.07 % ) " "Info: Total cell delay = 2.701 ns ( 27.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.277 ns ( 72.93 % ) " "Info: Total interconnect delay = 7.277 ns ( 72.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.978 ns" { reset center:inst|process0~0 center:inst|count[4] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "9.978 ns" { reset reset~out0 center:inst|process0~0 center:inst|count[4] } { 0.000ns 0.000ns 6.777ns 0.500ns } { 0.000ns 1.475ns 0.114ns 1.112ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "../center/center.vhd" "" { Text "D:/VHDL/trafic/center/center.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.569 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 12.569 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_J4 22 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 22; CLK Node = 'clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../fenwei/trafic.bdf" "" { Schematic "D:/VHDL/trafic/fenwei/trafic.bdf" { { 48 -376 -208 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns frequence1khz:inst3\|z 2 REG LC_X8_Y13_N2 20 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N2; Fanout = 20; REG Node = 'frequence1khz:inst3\|z'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.966 ns" { clk frequence1khz:inst3|z } "NODE_NAME" } } { "../fenpin/frequency1khz/frequence1khz.vhd" "" { Text "D:/VHDL/trafic/fenpin/frequency1khz/frequence1khz.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.619 ns) + CELL(0.935 ns) 7.989 ns frequency1hz:inst4\|z 3 REG LC_X9_Y13_N5 24 " "Info: 3: + IC(3.619 ns) + CELL(0.935 ns) = 7.989 ns; Loc. = LC_X9_Y13_N5; Fanout = 24; REG Node = 'frequency1hz:inst4\|z'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.554 ns" { frequence1khz:inst3|z frequency1hz:inst4|z } "NODE_NAME" } } { "../fenpin/frequency1hz/frequency1hz.vhd" "" { Text "D:/VHDL/trafic/fenpin/frequency1hz/frequency1hz.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.869 ns) + CELL(0.711 ns) 12.569 ns center:inst\|count\[4\] 4 REG LC_X32_Y11_N5 12 " "Info: 4: + IC(3.869 ns) + CELL(0.711 ns) = 12.569 ns; Loc. = LC_X32_Y11_N5; Fanout = 12; REG Node = 'center:inst\|count\[4\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.580 ns" { frequency1hz:inst4|z center:inst|count[4] } "NODE_NAME" } } { "../center/center.vhd" "" { Text "D:/VHDL/trafic/center/center.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 32.22 % ) " "Info: Total cell delay = 4.050 ns ( 32.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.519 ns ( 67.78 % ) " "Info: Total interconnect delay = 8.519 ns ( 67.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "12.569 ns" { clk frequence1khz:inst3|z frequency1hz:inst4|z center:inst|count[4] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "12.569 ns" { clk clk~out0 frequence1khz:inst3|z frequency1hz:inst4|z center:inst|count[4] } { 0.000ns 0.000ns 1.031ns 3.619ns 3.869ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.978 ns" { reset center:inst|process0~0 center:inst|count[4] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "9.978 ns" { reset reset~out0 center:inst|process0~0 center:inst|count[4] } { 0.000ns 0.000ns 6.777ns 0.500ns } { 0.000ns 1.475ns 0.114ns 1.112ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "12.569 ns" { clk frequence1khz:inst3|z frequency1hz:inst4|z center:inst|count[4] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "12.569 ns" { clk clk~out0 frequence1khz:inst3|z frequency1hz:inst4|z center:inst|count[4] } { 0.000ns 0.000ns 1.031ns 3.619ns 3.869ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk display\[6\] display:inst1\|count\[1\] 22.265 ns register " "Info: tco from clock \"clk\" to destination pin \"display\[6\]\" through register \"display:inst1\|count\[1\]\" is 22.265 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.732 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.732 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_J4 22 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 22; CLK Node = 'clk'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../fenwei/trafic.bdf" "" { Schematic "D:/VHDL/trafic/fenwei/trafic.bdf" { { 48 -376 -208 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns frequence1khz:inst3\|z 2 REG LC_X8_Y13_N2 20 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N2; Fanout = 20; REG Node = 'frequence1khz:inst3\|z'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.966 ns" { clk frequence1khz:inst3|z } "NODE_NAME" } } { "../fenpin/frequency1khz/frequence1khz.vhd" "" { Text "D:/VHDL/trafic/fenpin/frequency1khz/frequence1khz.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.586 ns) + CELL(0.711 ns) 7.732 ns display:inst1\|count\[1\] 3 REG LC_X28_Y14_N8 23 " "Info: 3: + IC(3.586 ns) + CELL(0.711 ns) = 7.732 ns; Loc. = LC_X28_Y14_N8; Fanout = 23; REG Node = 'display:inst1\|count\[1\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.297 ns" { frequence1khz:inst3|z display:inst1|count[1] } "NODE_NAME" } } { "../display/display.vhd" "" { Text "D:/VHDL/trafic/display/display.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.29 % ) " "Info: Total cell delay = 3.115 ns ( 40.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.617 ns ( 59.71 % ) " "Info: Total interconnect delay = 4.617 ns ( 59.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.732 ns" { clk frequence1khz:inst3|z display:inst1|count[1] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.732 ns" { clk clk~out0 frequence1khz:inst3|z display:inst1|count[1] } { 0.000ns 0.000ns 1.031ns 3.586ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "../display/display.vhd" "" { Text "D:/VHDL/trafic/display/display.vhd" 45 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.309 ns + Longest register pin " "Info: + Longest register to pin delay is 14.309 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns display:inst1\|count\[1\] 1 REG LC_X28_Y14_N8 23 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X28_Y14_N8; Fanout = 23; REG Node = 'display:inst1\|count\[1\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { display:inst1|count[1] } "NODE_NAME" } } { "../display/display.vhd" "" { Text "D:/VHDL/trafic/display/display.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.561 ns) + CELL(0.442 ns) 4.003 ns display:inst1\|display\[6\]~2469 2 COMB LC_X9_Y13_N1 1 " "Info: 2: + IC(3.561 ns) + CELL(0.442 ns) = 4.003 ns; Loc. = LC_X9_Y13_N1; Fanout = 1; COMB Node = 'display:inst1\|display\[6\]~2469'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.003 ns" { display:inst1|count[1] display:inst1|display[6]~2469 } "NODE_NAME" } } { "../display/display.vhd" "" { Text "D:/VHDL/trafic/display/display.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 4.299 ns display:inst1\|display\[6\]~2470 3 COMB LC_X9_Y13_N2 1 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 4.299 ns; Loc. = LC_X9_Y13_N2; Fanout = 1; COMB Node = 'display:inst1\|display\[6\]~2470'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { display:inst1|display[6]~2469 display:inst1|display[6]~2470 } "NODE_NAME" } } { "../display/display.vhd" "" { Text "D:/VHDL/trafic/display/display.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.991 ns) + CELL(0.292 ns) 7.582 ns display:inst1\|display\[6\]~2472 4 COMB LC_X29_Y12_N9 1 " "Info: 4: + IC(2.991 ns) + CELL(0.292 ns) = 7.582 ns; Loc. = LC_X29_Y12_N9; Fanout = 1; COMB Node = 'display:inst1\|display\[6\]~2472'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.283 ns" { display:inst1|display[6]~2470 display:inst1|display[6]~2472 } "NODE_NAME" } } { "../display/display.vhd" "" { Text "D:/VHDL/trafic/display/display.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.603 ns) + CELL(2.124 ns) 14.309 ns display\[6\] 5 PIN PIN_H3 0 " "Info: 5: + IC(4.603 ns) + CELL(2.124 ns) = 14.309 ns; Loc. = PIN_H3; Fanout = 0; PIN Node = 'display\[6\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.727 ns" { display:inst1|display[6]~2472 display[6] } "NODE_NAME" } } { "../fenwei/trafic.bdf" "" { Schematic "D:/VHDL/trafic/fenwei/trafic.bdf" { { 280 592 768 296 "display\[6..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.972 ns ( 20.77 % ) " "Info: Total cell delay = 2.972 ns ( 20.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.337 ns ( 79.23 % ) " "Info: Total interconnect delay = 11.337 ns ( 79.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "14.309 ns" { display:inst1|count[1] display:inst1|display[6]~2469 display:inst1|display[6]~2470 display:inst1|display[6]~2472 display[6] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "14.309 ns" { display:inst1|count[1] display:inst1|display[6]~2469 display:inst1|display[6]~2470 display:inst1|display[6]~2472 display[6] } { 0.000ns 3.561ns 0.182ns 2.991ns 4.603ns } { 0.000ns 0.442ns 0.114ns 0.292ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.732 ns" { clk frequence1khz:inst3|z display:inst1|count[1] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.732 ns" { clk clk~out0 frequence1khz:inst3|z display:inst1|count[1] } { 0.000ns 0.000ns 1.031ns 3.586ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "14.309 ns" { display:inst1|count[1] display:inst1|display[6]~2469 display:inst1|display[6]~2470 display:inst1|display[6]~2472 display[6] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "14.309 ns" { display:inst1|count[1] display:inst1|display[6]~2469 display:inst1|display[6]~2470 display:inst1|display[6]~2472 display[6] } { 0.000ns 3.561ns 0.182ns 2.991ns 4.603ns } { 0.000ns 0.442ns 0.114ns 0.292ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}