trafic.fit.smsg

fpga交通控制灯

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri Nov 14 19:42:00 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off trafic -c trafic
Info: Selected device EP1C12F324C8 for design "trafic"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 181 of 181 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1C4F324C8 is compatible
    Info: Device EP1C20F324C8 is compatible
Info: Fitter converted 2 user pins into dedicated programming pins
    Info: Pin ~nCSO~ is reserved at location J1
    Info: Pin ~ASDO~ is reserved at location K6
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "clk" to use Global clock in PIN J4
Info: Automatically promoted some destinations of signal "frequency1hz:inst4|z" to use Global clock
    Info: Destination "frequency1hz:inst4|z" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "frequence1khz:inst3|z" to use Global clock
    Info: Destination "frequence1khz:inst3|z" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 0.924 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X32_Y12; Fanout = 5; REG Node = 'center:inst|numa[3]'
    Info: 2: + IC(0.615 ns) + CELL(0.309 ns) = 0.924 ns; Loc. = LAB_X32_Y12; Fanout = 4; REG Node = 'fenwei:inst5|num_shi[0]'
    Info: Total cell delay = 0.309 ns ( 33.44 % )
    Info: Total interconnect delay = 0.615 ns ( 66.56 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%
    Info: The peak interconnect region extends from location X21_Y0 to location X31_Y13
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 1 warning
    Info: Allocated 181 megabytes of memory during processing
    Info: Processing ended: Fri Nov 14 19:42:05 2008
    Info: Elapsed time: 00:00:05