fenwei.tan.rpt

fpga交通控制灯

; N/A   ; None         ; 3.272 ns   ; numin[1] ; num_ge[3]~reg0  ; clk      ;
; N/A   ; None         ; 3.272 ns   ; numin[1] ; num_shi[0]~reg0 ; clk      ;
; N/A   ; None         ; 3.270 ns   ; numin[1] ; num_ge[2]~reg0  ; clk      ;
; N/A   ; None         ; 3.266 ns   ; numin[1] ; num_ge[1]~reg0  ; clk      ;
; N/A   ; None         ; 2.940 ns   ; numin[0] ; num_ge[0]~reg0  ; clk      ;
+-------+--------------+------------+----------+-----------------+----------+


+-------------------------------------------------------------------------------+
; tco                                                                           ;
+-------+--------------+------------+-----------------+------------+------------+
; Slack ; Required tco ; Actual tco ; From            ; To         ; From Clock ;
+-------+--------------+------------+-----------------+------------+------------+
; N/A   ; None         ; 9.107 ns   ; num_shi[0]~reg0 ; num_shi[0] ; clk        ;
; N/A   ; None         ; 8.612 ns   ; num_shi[1]~reg0 ; num_shi[1] ; clk        ;
; N/A   ; None         ; 7.107 ns   ; num_ge[2]~reg0  ; num_ge[2]  ; clk        ;
; N/A   ; None         ; 7.098 ns   ; num_ge[3]~reg0  ; num_ge[3]  ; clk        ;
; N/A   ; None         ; 7.053 ns   ; num_ge[1]~reg0  ; num_ge[1]  ; clk        ;
; N/A   ; None         ; 6.738 ns   ; num_ge[0]~reg0  ; num_ge[0]  ; clk        ;
+-------+--------------+------------+-----------------+------------+------------+


+---------------------------------------------------------------------------------+
; th                                                                              ;
+---------------+-------------+-----------+----------+-----------------+----------+
; Minimum Slack ; Required th ; Actual th ; From     ; To              ; To Clock ;
+---------------+-------------+-----------+----------+-----------------+----------+
; N/A           ; None        ; -2.888 ns ; numin[0] ; num_ge[0]~reg0  ; clk      ;
; N/A           ; None        ; -3.214 ns ; numin[1] ; num_ge[1]~reg0  ; clk      ;
; N/A           ; None        ; -3.218 ns ; numin[1] ; num_ge[2]~reg0  ; clk      ;
; N/A           ; None        ; -3.220 ns ; numin[1] ; num_ge[3]~reg0  ; clk      ;
; N/A           ; None        ; -3.220 ns ; numin[1] ; num_shi[0]~reg0 ; clk      ;
; N/A           ; None        ; -3.433 ns ; numin[3] ; num_shi[1]~reg0 ; clk      ;
; N/A           ; None        ; -3.437 ns ; numin[3] ; num_ge[1]~reg0  ; clk      ;
; N/A           ; None        ; -3.440 ns ; numin[3] ; num_ge[2]~reg0  ; clk      ;
; N/A           ; None        ; -3.442 ns ; numin[3] ; num_ge[3]~reg0  ; clk      ;
; N/A           ; None        ; -3.442 ns ; numin[3] ; num_shi[0]~reg0 ; clk      ;
; N/A           ; None        ; -3.675 ns ; numin[2] ; num_ge[3]~reg0  ; clk      ;
; N/A           ; None        ; -3.676 ns ; numin[2] ; num_ge[2]~reg0  ; clk      ;
; N/A           ; None        ; -3.676 ns ; numin[2] ; num_shi[0]~reg0 ; clk      ;
; N/A           ; None        ; -3.679 ns ; numin[2] ; num_ge[1]~reg0  ; clk      ;
; N/A           ; None        ; -3.680 ns ; numin[2] ; num_shi[1]~reg0 ; clk      ;
; N/A           ; None        ; -3.988 ns ; numin[4] ; num_shi[1]~reg0 ; clk      ;
; N/A           ; None        ; -3.989 ns ; numin[4] ; num_ge[2]~reg0  ; clk      ;
; N/A           ; None        ; -3.990 ns ; numin[4] ; num_ge[3]~reg0  ; clk      ;
; N/A           ; None        ; -3.991 ns ; numin[4] ; num_shi[0]~reg0 ; clk      ;
; N/A           ; None        ; -3.992 ns ; numin[4] ; num_ge[1]~reg0  ; clk      ;
+---------------+-------------+-----------+----------+-----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri Nov 14 17:12:38 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off fenwei -c fenwei --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: No valid register-to-register data paths exist for clock "clk"
Info: tsu for register "num_ge[1]~reg0" (data pin = "numin[4]", clock pin = "clk") is 4.044 ns
    Info: + Longest pin to register delay is 7.177 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_U3; Fanout = 5; PIN Node = 'numin[4]'
        Info: 2: + IC(5.095 ns) + CELL(0.607 ns) = 7.177 ns; Loc. = LC_X1_Y3_N4; Fanout = 1; REG Node = 'num_ge[1]~reg0'
        Info: Total cell delay = 2.082 ns ( 29.01 % )
        Info: Total interconnect delay = 5.095 ns ( 70.99 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.170 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(0.990 ns) + CELL(0.711 ns) = 3.170 ns; Loc. = LC_X1_Y3_N4; Fanout = 1; REG Node = 'num_ge[1]~reg0'
        Info: Total cell delay = 2.180 ns ( 68.77 % )
        Info: Total interconnect delay = 0.990 ns ( 31.23 % )
Info: tco from clock "clk" to destination pin "num_shi[0]" through register "num_shi[0]~reg0" is 9.107 ns
    Info: + Longest clock path from clock "clk" to source register is 3.170 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(0.990 ns) + CELL(0.711 ns) = 3.170 ns; Loc. = LC_X1_Y3_N5; Fanout = 1; REG Node = 'num_shi[0]~reg0'
        Info: Total cell delay = 2.180 ns ( 68.77 % )
        Info: Total interconnect delay = 0.990 ns ( 31.23 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 5.713 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y3_N5; Fanout = 1; REG Node = 'num_shi[0]~reg0'
        Info: 2: + IC(3.605 ns) + CELL(2.108 ns) = 5.713 ns; Loc. = PIN_B3; Fanout = 0; PIN Node = 'num_shi[0]'
        Info: Total cell delay = 2.108 ns ( 36.90 % )
        Info: Total interconnect delay = 3.605 ns ( 63.10 % )
Info: th for register "num_ge[0]~reg0" (data pin = "numin[0]", clock pin = "clk") is -2.888 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.246 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X1_Y18_N2; Fanout = 1; REG Node = 'num_ge[0]~reg0'
        Info: Total cell delay = 2.180 ns ( 67.16 % )
        Info: Total interconnect delay = 1.066 ns ( 32.84 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 6.149 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H3; Fanout = 1; PIN Node = 'numin[0]'
        Info: 2: + IC(4.565 ns) + CELL(0.115 ns) = 6.149 ns; Loc. = LC_X1_Y18_N2; Fanout = 1; REG Node = 'num_ge[0]~reg0'
        Info: Total cell delay = 1.584 ns ( 25.76 % )
        Info: Total interconnect delay = 4.565 ns ( 74.24 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 100 megabytes of memory during processing
    Info: Processing ended: Fri Nov 14 17:12:39 2008
    Info: Elapsed time: 00:00:01