fenwei.vhd

fpga交通控制灯

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity fenwei is
	port(clk : in std_logic;
		numin : in integer range 0 to 30;
		num_ge,num_shi :out integer range 0 to 9);
end entity;

architecture beha of fenwei is

begin
	process(clk)
	begin
		if(rising_edge(clk))then
			if(numin>=30)then
				num_ge<=numin-30;
				num_shi<=3;
			elsif(numin>=20)then
				num_ge<=numin-20;
				num_shi<=2;
			elsif (numin>=10)then
				num_ge<=numin-10;
				num_shi<=1;
			else
				num_ge<=numin;
				num_shi<=0;
			end if;
		end if;
	end process;
end architecture;