📄 frequency1hz.tan.rpt
字号:
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[1] ; z ; clk ; clk ; None ; None ; 3.049 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0] ; count[4] ; clk ; clk ; None ; None ; 3.018 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[3] ; count[7] ; clk ; clk ; None ; None ; 3.017 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[2] ; count[6] ; clk ; clk ; None ; None ; 3.016 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[2] ; count[3] ; clk ; clk ; None ; None ; 3.003 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[6] ; count[7] ; clk ; clk ; None ; None ; 2.992 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[3] ; count[2] ; clk ; clk ; None ; None ; 2.962 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[3] ; count[4] ; clk ; clk ; None ; None ; 2.959 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[3] ; count[6] ; clk ; clk ; None ; None ; 2.959 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[1] ; count[4] ; clk ; clk ; None ; None ; 2.931 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[3] ; count[8] ; clk ; clk ; None ; None ; 2.879 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[2] ; z ; clk ; clk ; None ; None ; 2.872 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0] ; count[2] ; clk ; clk ; None ; None ; 2.864 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[2] ; count[4] ; clk ; clk ; None ; None ; 2.852 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[1] ; count[2] ; clk ; clk ; None ; None ; 2.808 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[5] ; count[8] ; clk ; clk ; None ; None ; 2.796 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[7] ; count[2] ; clk ; clk ; None ; None ; 2.766 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[7] ; count[5] ; clk ; clk ; None ; None ; 2.766 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[7] ; count[7] ; clk ; clk ; None ; None ; 2.766 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[7] ; count[4] ; clk ; clk ; None ; None ; 2.765 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[7] ; count[6] ; clk ; clk ; None ; None ; 2.765 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0] ; count[1] ; clk ; clk ; None ; None ; 2.762 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[1] ; count[8] ; clk ; clk ; None ; None ; 2.725 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0] ; count[8] ; clk ; clk ; None ; None ; 2.676 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[2] ; count[2] ; clk ; clk ; None ; None ; 2.631 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[6] ; count[2] ; clk ; clk ; None ; None ; 2.566 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[6] ; count[5] ; clk ; clk ; None ; None ; 2.566 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[6] ; count[4] ; clk ; clk ; None ; None ; 2.565 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[6] ; count[6] ; clk ; clk ; None ; None ; 2.565 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[2] ; count[8] ; clk ; clk ; None ; None ; 2.548 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[7] ; count[8] ; clk ; clk ; None ; None ; 2.511 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[6] ; count[8] ; clk ; clk ; None ; None ; 2.504 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[3] ; count[3] ; clk ; clk ; None ; None ; 2.418 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0] ; z ; clk ; clk ; None ; None ; 2.308 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[1] ; count[1] ; clk ; clk ; None ; None ; 2.157 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[4] ; z ; clk ; clk ; None ; None ; 2.067 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0] ; count[0] ; clk ; clk ; None ; None ; 2.009 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[8] ; count[8] ; clk ; clk ; None ; None ; 1.617 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[5] ; z ; clk ; clk ; None ; None ; 1.612 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[8] ; count[6] ; clk ; clk ; None ; None ; 1.464 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[8] ; z ; clk ; clk ; None ; None ; 1.463 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[8] ; count[2] ; clk ; clk ; None ; None ; 1.462 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[8] ; count[7] ; clk ; clk ; None ; None ; 1.460 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[8] ; count[4] ; clk ; clk ; None ; None ; 1.458 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[7] ; z ; clk ; clk ; None ; None ; 1.327 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; z ; z ; clk ; clk ; None ; None ; 1.255 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[8] ; count[5] ; clk ; clk ; None ; None ; 1.177 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[6] ; z ; clk ; clk ; None ; None ; 1.127 ns ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
+-----------------------------------------------------------------+
; tco ;
+-------+--------------+------------+------+---------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+------+---------+------------+
; N/A ; None ; 6.879 ns ; z ; clk1khz ; clk ;
+-------+--------------+------------+------+---------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Fri Nov 14 12:04:17 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off frequency1hz -c frequency1hz --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 265.46 MHz between source register "count[4]" and destination register "count[2]" (period= 3.767 ns)
Info: + Longest register to register delay is 3.506 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y26_N8; Fanout = 3; REG Node = 'count[4]'
Info: 2: + IC(1.134 ns) + CELL(0.442 ns) = 1.576 ns; Loc. = LC_X12_Y26_N2; Fanout = 7; COMB Node = 'Equal0~81'
Info: 3: + IC(1.192 ns) + CELL(0.738 ns) = 3.506 ns; Loc. = LC_X12_Y26_N4; Fanout = 4; REG Node = 'count[2]'
Info: Total cell delay = 1.180 ns ( 33.66 % )
Info: Total interconnect delay = 2.326 ns ( 66.34 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 3.246 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 10; CLK Node = 'clk'
Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X12_Y26_N4; Fanout = 4; REG Node = 'count[2]'
Info: Total cell delay = 2.180 ns ( 67.16 % )
Info: Total interconnect delay = 1.066 ns ( 32.84 % )
Info: - Longest clock path from clock "clk" to source register is 3.246 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 10; CLK Node = 'clk'
Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X12_Y26_N8; Fanout = 3; REG Node = 'count[4]'
Info: Total cell delay = 2.180 ns ( 67.16 % )
Info: Total interconnect delay = 1.066 ns ( 32.84 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "clk" to destination pin "clk1khz" through register "z" is 6.879 ns
Info: + Longest clock path from clock "clk" to source register is 3.246 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 10; CLK Node = 'clk'
Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X12_Y26_N3; Fanout = 2; REG Node = 'z'
Info: Total cell delay = 2.180 ns ( 67.16 % )
Info: Total interconnect delay = 1.066 ns ( 32.84 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Longest register to pin delay is 3.409 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y26_N3; Fanout = 2; REG Node = 'z'
Info: 2: + IC(1.301 ns) + CELL(2.108 ns) = 3.409 ns; Loc. = PIN_E6; Fanout = 0; PIN Node = 'clk1khz'
Info: Total cell delay = 2.108 ns ( 61.84 % )
Info: Total interconnect delay = 1.301 ns ( 38.16 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
Info: Allocated 101 megabytes of memory during processing
Info: Processing ended: Fri Nov 14 12:04:18 2008
Info: Elapsed time: 00:00:01
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