frequence1khz.fit.rpt

fpga交通控制灯

; Auto Global Memory Control Signals                 ; Off                            ; Off                            ;
; Auto Packed Registers -- Cyclone                   ; Auto                           ; Auto                           ;
; Auto Delay Chains                                  ; On                             ; On                             ;
; Auto Merge PLLs                                    ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic ; Off                            ; Off                            ;
; Perform Register Duplication                       ; Off                            ; Off                            ;
; Perform Register Retiming                          ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining             ; Off                            ; Off                            ;
; Fitter Effort                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                    ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication           ; Auto                           ; Auto                           ;
; Auto Register Duplication                          ; Auto                           ; Auto                           ;
; Auto Global Clock                                  ; On                             ; On                             ;
; Auto Global Register Control Signals               ; On                             ; On                             ;
; Stop After Congestion Map Generation               ; Off                            ; Off                            ;
; Use smart compilation                              ; Off                            ; Off                            ;
+----------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/VHDL/trafic/fenpin/frequency1khz/frequence1khz.pin.


+---------------------------------------------------------------------+
; Fitter Resource Usage Summary                                       ;
+---------------------------------------------+-----------------------+
; Resource                                    ; Usage                 ;
+---------------------------------------------+-----------------------+
; Total logic elements                        ; 20 / 12,060 ( < 1 % ) ;
;     -- Combinational with no register       ; 10                    ;
;     -- Register only                        ; 2                     ;
;     -- Combinational with a register        ; 8                     ;
;                                             ;                       ;
; Logic element usage by number of LUT inputs ;                       ;
;     -- 4 input functions                    ; 9                     ;
;     -- 3 input functions                    ; 0                     ;
;     -- 2 input functions                    ; 8                     ;
;     -- 1 input functions                    ; 2                     ;
;     -- 0 input functions                    ; 1                     ;
;                                             ;                       ;
; Logic elements by mode                      ;                       ;
;     -- normal mode                          ; 12                    ;
;     -- arithmetic mode                      ; 8                     ;
;     -- qfbk mode                            ; 1                     ;
;     -- register cascade mode                ; 0                     ;
;     -- synchronous clear/load mode          ; 2                     ;
;     -- asynchronous clear/load mode         ; 0                     ;
;                                             ;                       ;
; Total registers                             ; 10 / 12,795 ( < 1 % ) ;
; Total LABs                                  ; 2 / 1,206 ( < 1 % )   ;
; Logic elements in carry chains              ; 9                     ;
; User inserted logic elements                ; 0                     ;
; Virtual pins                                ; 0                     ;
; I/O pins                                    ; 2 / 249 ( < 1 % )     ;
;     -- Clock pins                           ; 1 / 2 ( 50 % )        ;
; Global signals                              ; 1                     ;
; M4Ks                                        ; 0 / 52 ( 0 % )        ;
; Total memory bits                           ; 0 / 239,616 ( 0 % )   ;
; Total RAM block bits                        ; 0 / 239,616 ( 0 % )   ;
; PLLs                                        ; 0 / 2 ( 0 % )         ;
; Global clocks                               ; 1 / 8 ( 13 % )        ;
; Average interconnect usage                  ; 0%                    ;
; Peak interconnect usage                     ; 0%                    ;
; Maximum fan-out node                        ; clk                   ;
; Maximum fan-out                             ; 10                    ;
; Highest non-global fan-out signal           ; count[8]              ;
; Highest non-global fan-out                  ; 8                     ;
; Total fan-out                               ; 69                    ;
; Average fan-out                             ; 2.88                  ;
+---------------------------------------------+-----------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                 ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; clk  ; J4    ; 1        ; 0            ; 14           ; 0           ; 10                    ; 0                  ; yes    ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; Fitter               ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                                                ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+
; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load  ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+
; clk1khz ; E6    ; 2        ; 12           ; 27           ; 2           ; no              ; no                     ; no            ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 24mA             ; Off         ; Fitter               ; 10 pF ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+


+----------------------------------------------------------+
; I/O Bank Usage                                           ;
+----------+----------------+---------------+--------------+
; I/O Bank ; Usage          ; VCCIO Voltage ; VREF Voltage ;
+----------+----------------+---------------+--------------+
; 1        ; 3 / 63 ( 5 % ) ; 3.3V          ; --           ;
; 2        ; 1 / 61 ( 2 % ) ; 3.3V          ; --           ;