📄 bahf.asm
字号:
;XSFR
INTEN1 EQU 0F04H
ADC EQU 0F10H ;R/W BIT7(ENADC),BIT3((SADC3),BIT2(SADC2),BIT1(SADC1),BIT0(SADC0)
;READ ADC VALUE
WDT EQU 0F18H ; /W BIT7(WEN),BIT6(Wclr),BIT2(WDT2),BIT1(WDT1),BIT0(WDT0)
DA0 EQU 0F20H ;R/W
DA1 EQU 0F21H ;R/W
DA2 EQU 0F22H ;R/W
DA3 EQU 0F23H ;R/W
PADMOD1 EQU 0F2BH ;/W BIT7(HIICE) "0" P3.0/RXD & P3.1/TXD,"1" HSCL & HSDA
; BIT6(LIICE) "0" P6.0 & P6.1,"1" LSCL & LSDA
; BIT5(HVE) "0" P4.6 & P4.7,"1" HBLANK & VBLANK
; BIT4(HclpE) "0" P4.5,"1" HCLAMP
; BIT1(FclkE) "0" NORMAL RATE,"1" DOUBLE RATE
; BIT0(P62E) "0" INT,"1" P62
PADMOD2 EQU 0F2CH ;/W BIT7(DA3E) "0" P5.7,"1" DA3
; BIT6(DA2E) "0" P5.6,"1" DA2
; BIT5(DA1E) "0" P5.5,"1" DA1
; BIT4(DA0E) "0" P5.4,"1" DA0
; BIT3(AD3E) "0" P5.3,"1" AD3
; BIT2(AD2E) "0" P5.2,"1" AD2
; BIT1(AD1E) "0" P5.1,"1" AD1
; BIT0(AD0E) "0" P5.0,"1" AD0
PADMOD3 EQU 0F2DH ;/W "0" INPUT,"1" OUTPUT,P4.7---P4.0
PADMOD4 EQU 0F2EH ;/W "0" INPUT,"1" OUTPUT,P5.7---P5.0
OPTION EQU 0F2FH ;/W BIT7(PWMF) "0" 47KHz PWM,"1" 94KHz PWM
; BIT6(DIV253)"0" 256 STEP,"1" 253 STEP
; BIT5(SlvAbs1),BIT4(SlvAbs0),slave IIC block A's slave address length
; =1'0 5-BIT slave address,=0'1 6-BIT,=0'0 7-BIT
; BIT3(ENSCL),ENABLE slave IIC block hold HSCL low while ex-master H-speed
; BIT2(Msel) "0" MASTR IIC BLOCK CONNECT TO HSCL/HSDA
; "1" MASTR IIC BLOCK CONNECT TO LSCL/LSDA
; BIT1(MIICF1),BIT0(MIICF0),=1'1 MASTER IIC 400KHz,=1'0 200KHz,=0'1 50KHz,=0'0 100KHz
P40 EQU 0F30H ;R/W BIT0 valid
P41 EQU 0F31H ;R/W BIT0 valid
P42 EQU 0F32H ;R/W BIT0 valid
P43 EQU 0F33H ;R/W BIT0 valid
P44 EQU 0F34H ;R/W BIT0 valid
P45 EQU 0F35H ;R/W BIT0 valid
P46 EQU 0F36H ;R/W BIT0 valid
P47 EQU 0F37H ;R/W BIT0 valid
P50 EQU 0F38H ;R/W BIT0 valid
P51 EQU 0F39H ;R/W BIT0 valid
P52 EQU 0F3AH ;R/W BIT0 valid
P53 EQU 0F3BH ;R/W BIT0 valid
P54 EQU 0F3CH ;R/W BIT0 valid
P55 EQU 0F3DH ;R/W BIT0 valid
P56 EQU 0F3EH ;R/W BIT0 valid
P57 EQU 0F3FH ;R/W BIT0 valid
P60 EQU 0F28H ;R/W BIT0 valid
P61 EQU 0F29H ;R/W BIT0 valid
P62 EQU 0F2AH ;R/W BIT0 valid
HVSTUS EQU 0F40H ;R/ BIT7(CVpre),BIT5(Hpol),BIT4(Vpol),BIT3(Hpre),BIT2(Vpre),BIT1(Hoff),BIT0(voff)
HCNTH EQU 0F41H ;R/ BIT7(Hovf) H OVER FLAG,BIT5(HF13),BIT4(HF12),BIT3(HF11),BIT2(HF10),BIT1(HF9),BIT0(HF8)
HCNTL EQU 0F42H ;R/ H-FREQUENCE COUNTER LOW BYTE,HF7---HF0
VCNTH EQU 0F43H ;R/ BIT7(Vovf) V OVER FLAG,BIT3(VF11),BIT2(VF10),BIT1(VF9),BIT0(VF8)
VCNTL EQU 0F44H ;R/ V-FREQUENCE COUNTER LOW BYTE,VF7---VF0
HVCTR0 EQU 0F40H ;/W BIT7(C1),BIT6(C0),C1'C0=1'1,SELECT CVSYNC AS THE POLARITY,FREQ AND VBLANK SOURCE
; C1'C0=1'0,SELECT VSYNC AS THE POLARITY,FREQ AND VBLANK SOURCE
; C1'C0=0'0,DISABLE COMPOSITE FUNCTION
; C1'C0=0'1,H/W AUTO SWITCH TO CVBLANK WHEN CVpre=1 & VSpre=0
; BIT5(NOHINS)"0" HBLANK INSERT PULSE IN CV,"1" HBLANK INSERT PULSE NO IN CV
; BIT1(HBpl) "0" HBLANK POSITIVE POLARITY OUT,"1" HBLANK NEGATIVE
; BIT0(VBpl) "0" VBLANK POSITIVE POLARITY OUT,"1" VBLANK NEGATIVE
HVCTR3 EQU 0F43H ; BIT6(CLPEG) "0" CLAMP PULSE FOLLOW Hsync TRAILING EDGE,"1" LEADING EDGE
; BIT5(CLPPO) "0" NEGATIVE POLARITY CLAMP PULSE OUT,"1" POSITIVE
INTFLG EQU 0F48H ;R/W BIT7(HPRchg)"0" /W CLEAR Hsync PRESENCE CHANGE FLAG,"1" R/ INDICATE A Hsync PRESENCE CHANGE
; BIT6(VPRchg)"0" /W CLEAR Vsync PRESENCE CHANGE FLAG,"1" R/ INDICATE A Vsync PRESENCE CHANGE
; BIT5(HPLchg)"0" /W CLEAR Hsync POLARITY CHANGE FLAG,"1" R/ INDICATE A Hsync POLARITY CHANGE
; BIT4(VPLchg)"0" /W CLEAR Vsync POLARITY CHANGE FLAG,"1" R/ INDICATE A Vsync POLARITY CHANGE
; BIT3(HFchg) "0" /W CLEAR Hsync FREQUENCY CHANGE FLAG,"1" R/ INDICATE A Hsync FREQUENCY CHANGE
; BIT2(VFchg) "0" /W CLEAR Vsync FREQUENCY CHANGE FLAG,"1" R/ INDICATE A Vsync FREQUENCY CHANGE
; BIT0(Vsync) "0" /W CLEAR Vsync INTERRUPT FLAG,"1" R/ INDICATE A Vsync INTERRUPT
INTEN2 EQU 0F49H ;/W BIT7(EHpr) "1" ENABLE Hsync PRESENCE CHANGE INTERRUPT
; BIT6(EVpr) "1" ENABLE Vsync PRESENCE CHANGE INTERRUPT
; BIT5(EHpl) "1" ENABLE Hsync POLARITY CHANGE INTERRUPT
; BIT4(EVpl) "1" ENABLE Vsync POLARITY CHANGE INTERRUPT
; BIT3(EHF) "1" ENABLE Hsync FREQUENCY CHANGE/COUNTER OVERFLOW INTERRUPT
; BIT2(EVF) "1" ENABLE Vsync FREQUENCY CHANGE/COUNTER OVERFLOW INTERRUPT
; BIT0(EVsync)"1" ENABLE Vsync INTERRUPT
OSDRA EQU 0FA0H ; /W BIT7,BIT6:"0,0" ADDRES BYTE,"0,1" ATTRIBUTE BYTE,BIT3-BIT0,ROW0-14
OSDCA EQU 0FA1H ; /W BIT4-BIT0,COLUMN0-29
OSDDT0 EQU 0FA2H ; /W BIT7-BIT0,8 BIT LSB FONT ADDRES OR ATTRIBUTE,BIT8(MSB):0, FIX,0-255
OSDDT1 EQU 0FA3H ; /W BIT7-BIT0,8 BIT LSB FONT ADDRES OR ATTRIBUTE,BIT8(MSB):1, FIX,256-511
W1ROW EQU 0FC0H ;
W1COL1 EQU 0FC1H ;
W1COL2 EQU 0FC2H ;
VERTD EQU 0FCCH ; /W VERTICAL START POSITION REGISTER
HORD EQU 0FCDH ; /W Horizontal START POSITION REGISTER
CH EQU 0FCEH ; /W BIT6-BIT0 CHARACTER HEIGHT
RSPACE EQU 0FD0H ; /W BIT4-BIT0 ROW TO ROW SPACING
OSDCON1 EQU 0FD1H ;R/W BIT7(OSDEN),BIT6(BSEN)-BORDERING OR SHADOWING EFFECT
; BIT5(SHADOW)"1" SHADOWING EFFECT,"0" BORDERING EFFECT
; BIT4(FBEN) FADE-IN/FADE-OUT OR BLENDING-IN/BLENDING-OUT EFFECT
; BIT3(BLEND) "1" BLENDING-IN/BLENDING-OUT EFFECT,"0" FADE-IN/FADE-OUT EFFECT
; BIT2(WENclr)"1" CLEAR ALL WEN BITS OF WINDOW CONTROL REGISTERS
; BIT1(RAMclr)"1" CLEAR ALL ADDRESS BYTES,BGR,BGG,BGB,BLINK OF DISPLAY RAM
; BIT0(FBKGC) "1" PIN FBKG OUTPUTS HIGH ONLY CHARACTERS,"0" PIN HIGH CHARACTERS OR WINDOW
OSDCON2 EQU 0FD2H ;R/W BIT4(DWE) "1" ENABLE DOUBLE WIDTH
; BIT3(HSP) "1" POSITIVE POLARITY OSDHS INPUT,"0" NEGATIVE POLARITY OSDHS INPUT
; BIT2(VSP) "1" POSITIVE POLARITY OSDVS INPUT,"0" NEGATIVE POLARITY OSDVS INPUT
CSHADOW EQU 0FD3H ; /W BIT2(CSR)-R,BIT1(CSG)-G,BIT0(CSB)-B
FSCREEN EQU 0FD4H ; /W BIT7(FSW) ENABLE FULL SCREEN SEFT-TEST PATTERN,FORCE FBKG HIGH TO DISPLAY RGB
; BIT2(FSR)-R,BIT1(FSG)-G,BIT0(FSB)-B
WINSW EQU 0FD5H ; /W BIT7(WW41),BIT6(WW40),BIT5(WW31),BIT4(WW30),BIT3(WW21),BIT2(WW20),BIT1(WW11),BIT0(WW10)
WINSH EQU 0FD6H ; /W BIT7(WH41),BIT6(WH40),BIT5(WH31),BIT4(WH30),BIT3(WH21),BIT2(WH20),BIT1(WH11),BIT0(WH10)
WINSC1 EQU 0FD7H ; /W WINDOW SHADOW COLOR BIT6(R1),BIT5(G1),BIT4(B1),BIT2(R2),BIT1(G2),BIT0(B2)
WINSC2 EQU 0FD8H ; /W WINDOW SHADOW COLOR BIT6(R3),BIT5(G3),BIT4(B3),BIT2(R4),BIT1(G4),BIT0(B4)
XDEL EQU 0FD9H ; /W
check1 equ 30h
check2 equ 3fh
;=====================================================
;MAIN PROGRAM
;-----------------------------------------------------
ORG 0000H
AJMP START
ORG 0003H ;EXTER INTERRUPT0
RETI
ORG 000BH ;TIMER INTERRUPT0
RETI
ORG 0013H ;EXTER INTERRUPT1
RETI
ORG 001BH ;TIMER INTERRUPT1
RETI
ORG 0023H ;SERIAL INTERRUPT
RETI
;-----------------------------------------------------
ORG 200H
START:
CLR EA
MOV DPTR,#WDT
MOV A,#40H
MOVX @DPTR,A
MOV DPTR,#INTEN1
MOV A,#0
MOVX @DPTR,A
MOV DPTR,#INTEN2
MOV A,#0
MOVX @DPTR,A
MOV CHECK1,#55H
MOV CHECK2,#0AAH
MOV P1,#0FFH ;
MOV P3,#0FFH ;
MOV TMOD,#0 ;TIMER0--WORK ON MODE 1,TIMER1--WORK ON MODE 0
MOV TCON,#0 ;CLEAR TCON
MOV SP,#70H ;STACK 70H START
MOV PSW,#0 ;CLEAR PSW
MOV DPTR,#PADMOD1 ;SELECT P3.0,P3.1,P6.0,P6.1,HBLABK,VBLANK,P4.5,CPU=12M,P6.2
MOV A,#00101100B
MOVX @DPTR,A
MOV DPTR,#PADMOD2 ;SELECT P5.7,P5.6,P5.5,P5.4,P5.3,P5.2,P5.1,P5.0
MOV A,#00000000B
MOVX @DPTR,A
MOV DPTR,#PADMOD3 ;SELECT P4 OUTPUT
MOV A,#00111100B
MOVX @DPTR,A
MOV DPTR,#PADMOD4 ;SELECT P5 OUTPUT
MOV A,#11111111B
MOVX @DPTR,A
MOV DPTR,#OPTION ;暂时不选
MOV A,#00000000B
MOVX @DPTR,A
MOV DPTR,#OSDCON1 ;OSD ENABLE
MOV A,#10000110B
MOVX @DPTR,A
ACALL DELAY1
MOV DPTR,#OSDCON1 ;OSD ENABLE
MOV A,#10000000B
MOVX @DPTR,A
MOV DPTR,#OSDCON2 ;ACCEPT NEGATIVE OSDHS AND OSDVS INPUT
MOV A,#10H ; ; Polarity(OSDHS/OSDVS) OSDCON2
MOVX @DPTR,A ; +/+ 0x1c
MOV DPTR,#VERTD ;+/- 0x18 (0x1a)
MOV A,#4 ;-/+ 0x14
MOVX @DPTR,A ;-/- 0x10
MOV DPTR,#HORD
MOV A,#68
MOVX @DPTR,A
MOV DPTR,#CH
MOV A,#0
MOVX @DPTR,A
MOV DPTR,#RSPACE
MOV A,#0
MOVX @DPTR,A
MOV DPTR,#XDEL
MOV A,#10
MOVX @DPTR,A
MOV DPTR,#FSCREEN ;SELF-TEST
MOV A,#81H
MOVX @DPTR,A
ACALL DELAY2
MOV DPTR,#FSCREEN ;SELF-TEST
MOV A,#00H
MOVX @DPTR,A
;.................................................
MAIN:
MOV DPTR,#W1ROW
MOV A,#0DH
MOVX @DPTR,A
MOV DPTR,#W1COL1
MOV A,#05H
MOVX @DPTR,A
MOV DPTR,#W1COL2
MOV A,#0FAH
MOVX @DPTR,A
MOV DPTR,#WINSW
MOV A,#01H
MOVX @DPTR,A
MOV DPTR,#WINSH
MOV A,#01H
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