hour.tan.rpt

vhdl语言

; N/A   ; 103.09 MHz ( period = 9.700 ns )               ; count[2] ; count[5] ; clk        ; clk      ; None                        ; None                      ; 7.500 ns                ;
; N/A   ; 103.09 MHz ( period = 9.700 ns )               ; count[1] ; count[4] ; clk        ; clk      ; None                        ; None                      ; 7.500 ns                ;
; N/A   ; 105.26 MHz ( period = 9.500 ns )               ; count[3] ; count[5] ; clk        ; clk      ; None                        ; None                      ; 7.300 ns                ;
; N/A   ; 105.26 MHz ( period = 9.500 ns )               ; count[2] ; count[4] ; clk        ; clk      ; None                        ; None                      ; 7.300 ns                ;
; N/A   ; 105.26 MHz ( period = 9.500 ns )               ; count[1] ; count[3] ; clk        ; clk      ; None                        ; None                      ; 7.300 ns                ;
; N/A   ; 107.53 MHz ( period = 9.300 ns )               ; count[4] ; count[5] ; clk        ; clk      ; None                        ; None                      ; 7.100 ns                ;
; N/A   ; 107.53 MHz ( period = 9.300 ns )               ; count[3] ; count[4] ; clk        ; clk      ; None                        ; None                      ; 7.100 ns                ;
; N/A   ; 107.53 MHz ( period = 9.300 ns )               ; count[2] ; count[3] ; clk        ; clk      ; None                        ; None                      ; 7.100 ns                ;
; N/A   ; 107.53 MHz ( period = 9.300 ns )               ; count[1] ; count[2] ; clk        ; clk      ; None                        ; None                      ; 7.100 ns                ;
; N/A   ; 108.70 MHz ( period = 9.200 ns )               ; count[4] ; count[4] ; clk        ; clk      ; None                        ; None                      ; 7.000 ns                ;
; N/A   ; 108.70 MHz ( period = 9.200 ns )               ; count[3] ; count[3] ; clk        ; clk      ; None                        ; None                      ; 7.000 ns                ;
; N/A   ; 108.70 MHz ( period = 9.200 ns )               ; count[2] ; count[2] ; clk        ; clk      ; None                        ; None                      ; 7.000 ns                ;
; N/A   ; 108.70 MHz ( period = 9.200 ns )               ; count[1] ; count[1] ; clk        ; clk      ; None                        ; None                      ; 7.000 ns                ;
; N/A   ; 114.94 MHz ( period = 8.700 ns )               ; count[5] ; count[5] ; clk        ; clk      ; None                        ; None                      ; 6.500 ns                ;
; N/A   ; 119.05 MHz ( period = 8.400 ns )               ; count[0] ; count[3] ; clk        ; clk      ; None                        ; None                      ; 6.200 ns                ;
; N/A   ; 121.95 MHz ( period = 8.200 ns )               ; count[0] ; count[2] ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 125.00 MHz ( period = 8.000 ns )               ; count[0] ; count[1] ; clk        ; clk      ; None                        ; None                      ; 5.800 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; count[4] ; count[3] ; clk        ; clk      ; None                        ; None                      ; 4.500 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; count[3] ; count[2] ; clk        ; clk      ; None                        ; None                      ; 4.500 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; count[4] ; count[2] ; clk        ; clk      ; None                        ; None                      ; 4.500 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; count[2] ; count[1] ; clk        ; clk      ; None                        ; None                      ; 4.500 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; count[3] ; count[1] ; clk        ; clk      ; None                        ; None                      ; 4.500 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; count[4] ; count[1] ; clk        ; clk      ; None                        ; None                      ; 4.500 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; count[5] ; count[4] ; clk        ; clk      ; None                        ; None                      ; 4.000 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; count[5] ; count[3] ; clk        ; clk      ; None                        ; None                      ; 4.000 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; count[5] ; count[2] ; clk        ; clk      ; None                        ; None                      ; 4.000 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; count[5] ; count[1] ; clk        ; clk      ; None                        ; None                      ; 4.000 ns                ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------------+
; tco                                                                  ;
+-------+--------------+------------+----------+----------+------------+
; Slack ; Required tco ; Actual tco ; From     ; To       ; From Clock ;
+-------+--------------+------------+----------+----------+------------+
; N/A   ; None         ; 10.900 ns  ; count[0] ; daout[0] ; clk        ;
; N/A   ; None         ; 10.100 ns  ; count[5] ; daout[5] ; clk        ;
; N/A   ; None         ; 10.100 ns  ; count[4] ; daout[4] ; clk        ;
; N/A   ; None         ; 10.100 ns  ; count[3] ; daout[3] ; clk        ;
; N/A   ; None         ; 10.100 ns  ; count[2] ; daout[2] ; clk        ;
; N/A   ; None         ; 10.100 ns  ; count[1] ; daout[1] ; clk        ;
+-------+--------------+------------+----------+----------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Tue Oct 28 17:06:19 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off hour -c hour
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 89.29 MHz between source register "count[0]" and destination register "count[0]" (period= 11.2 ns)
    Info: + Longest register to register delay is 9.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A14; Fanout = 5; REG Node = 'count[0]'
        Info: 2: + IC(1.900 ns) + CELL(1.900 ns) = 3.800 ns; Loc. = LC7_A13; Fanout = 6; COMB Node = 'rtl~28'
        Info: 3: + IC(0.600 ns) + CELL(1.400 ns) = 5.800 ns; Loc. = LC2_A13; Fanout = 1; COMB Node = 'count~499'
        Info: 4: + IC(1.800 ns) + CELL(1.400 ns) = 9.000 ns; Loc. = LC1_A14; Fanout = 5; REG Node = 'count[0]'
        Info: Total cell delay = 4.700 ns ( 52.22 % )
        Info: Total interconnect delay = 4.300 ns ( 47.78 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.900 ns
            Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_A14; Fanout = 5; REG Node = 'count[0]'
            Info: Total cell delay = 1.900 ns ( 48.72 % )
            Info: Total interconnect delay = 2.000 ns ( 51.28 % )
        Info: - Longest clock path from clock "clk" to source register is 3.900 ns
            Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_A14; Fanout = 5; REG Node = 'count[0]'
            Info: Total cell delay = 1.900 ns ( 48.72 % )
            Info: Total interconnect delay = 2.000 ns ( 51.28 % )
    Info: + Micro clock to output delay of source is 0.900 ns
    Info: + Micro setup delay of destination is 1.300 ns
Info: tco from clock "clk" to destination pin "daout[0]" through register "count[0]" is 10.900 ns
    Info: + Longest clock path from clock "clk" to source register is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_A14; Fanout = 5; REG Node = 'count[0]'
        Info: Total cell delay = 1.900 ns ( 48.72 % )
        Info: Total interconnect delay = 2.000 ns ( 51.28 % )
    Info: + Micro clock to output delay of source is 0.900 ns
    Info: + Longest register to pin delay is 6.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A14; Fanout = 5; REG Node = 'count[0]'
        Info: 2: + IC(2.200 ns) + CELL(3.900 ns) = 6.100 ns; Loc. = PIN_16; Fanout = 0; PIN Node = 'daout[0]'
        Info: Total cell delay = 3.900 ns ( 63.93 % )
        Info: Total interconnect delay = 2.200 ns ( 36.07 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Oct 28 17:06:19 2008
    Info: Elapsed time: 00:00:01