second.tan.rpt

vhdl语言

; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; count[5]   ; count[3]   ; clk        ; clk      ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; count[6]   ; count[3]   ; clk        ; clk      ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; count[5]   ; count[2]   ; clk        ; clk      ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; count[6]   ; count[2]   ; clk        ; clk      ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; count[2]   ; count[1]   ; clk        ; clk      ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; count[5]   ; count[1]   ; clk        ; clk      ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; count[6]   ; count[1]   ; clk        ; clk      ; None                        ; None                      ; 5.500 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; enmin~reg0 ; enmin~reg0 ; clk        ; clk      ; None                        ; None                      ; 4.000 ns                ;
+-------+------------------------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------------+
; tsu                                                                ;
+-------+--------------+------------+--------+------------+----------+
; Slack ; Required tsu ; Actual tsu ; From   ; To         ; To Clock ;
+-------+--------------+------------+--------+------------+----------+
; N/A   ; None         ; 2.400 ns   ; setmin ; count[1]   ; clk      ;
; N/A   ; None         ; 2.400 ns   ; setmin ; count[2]   ; clk      ;
; N/A   ; None         ; 2.400 ns   ; setmin ; count[5]   ; clk      ;
; N/A   ; None         ; 2.400 ns   ; setmin ; count[6]   ; clk      ;
; N/A   ; None         ; 2.400 ns   ; setmin ; count[3]   ; clk      ;
; N/A   ; None         ; 2.400 ns   ; setmin ; count[4]   ; clk      ;
; N/A   ; None         ; 2.400 ns   ; setmin ; count[0]   ; clk      ;
; N/A   ; None         ; 2.000 ns   ; reset  ; enmin~reg0 ; clk      ;
+-------+--------------+------------+--------+------------+----------+


+------------------------------------------------------------------------+
; tco                                                                    ;
+-------+--------------+------------+------------+----------+------------+
; Slack ; Required tco ; Actual tco ; From       ; To       ; From Clock ;
+-------+--------------+------------+------------+----------+------------+
; N/A   ; None         ; 10.900 ns  ; count[5]   ; daout[5] ; clk        ;
; N/A   ; None         ; 10.900 ns  ; count[1]   ; daout[1] ; clk        ;
; N/A   ; None         ; 10.900 ns  ; count[0]   ; daout[0] ; clk        ;
; N/A   ; None         ; 10.300 ns  ; count[6]   ; daout[6] ; clk        ;
; N/A   ; None         ; 10.100 ns  ; count[4]   ; daout[4] ; clk        ;
; N/A   ; None         ; 10.100 ns  ; count[2]   ; daout[2] ; clk        ;
; N/A   ; None         ; 10.000 ns  ; enmin~reg0 ; enmin    ; clk        ;
; N/A   ; None         ; 9.600 ns   ; count[3]   ; daout[3] ; clk        ;
+-------+--------------+------------+------------+----------+------------+


+--------------------------------------------------------------------------+
; th                                                                       ;
+---------------+-------------+-----------+--------+------------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To         ; To Clock ;
+---------------+-------------+-----------+--------+------------+----------+
; N/A           ; None        ; 0.700 ns  ; reset  ; enmin~reg0 ; clk      ;
; N/A           ; None        ; 0.300 ns  ; setmin ; count[1]   ; clk      ;
; N/A           ; None        ; 0.300 ns  ; setmin ; count[2]   ; clk      ;
; N/A           ; None        ; 0.300 ns  ; setmin ; count[5]   ; clk      ;
; N/A           ; None        ; 0.300 ns  ; setmin ; count[6]   ; clk      ;
; N/A           ; None        ; 0.300 ns  ; setmin ; count[3]   ; clk      ;
; N/A           ; None        ; 0.300 ns  ; setmin ; count[4]   ; clk      ;
; N/A           ; None        ; 0.300 ns  ; setmin ; count[0]   ; clk      ;
+---------------+-------------+-----------+--------+------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Tue Oct 28 16:51:46 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off second -c second
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 73.53 MHz between source register "count[1]" and destination register "count[4]" (period= 13.6 ns)
    Info: + Longest register to register delay is 11.400 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_A15; Fanout = 5; REG Node = 'count[1]'
        Info: 2: + IC(0.600 ns) + CELL(1.900 ns) = 2.500 ns; Loc. = LC1_A15; Fanout = 3; COMB Node = 'rtl~59'
        Info: 3: + IC(1.800 ns) + CELL(1.900 ns) = 6.200 ns; Loc. = LC2_A13; Fanout = 4; COMB Node = 'count~688'
        Info: 4: + IC(1.800 ns) + CELL(1.900 ns) = 9.900 ns; Loc. = LC1_A14; Fanout = 1; COMB Node = 'count~692'
        Info: 5: + IC(0.600 ns) + CELL(0.900 ns) = 11.400 ns; Loc. = LC8_A14; Fanout = 6; REG Node = 'count[4]'
        Info: Total cell delay = 6.600 ns ( 57.89 % )
        Info: Total interconnect delay = 4.800 ns ( 42.11 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.900 ns
            Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'clk'
            Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC8_A14; Fanout = 6; REG Node = 'count[4]'
            Info: Total cell delay = 1.900 ns ( 48.72 % )
            Info: Total interconnect delay = 2.000 ns ( 51.28 % )
        Info: - Longest clock path from clock "clk" to source register is 3.900 ns
            Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'clk'
            Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC3_A15; Fanout = 5; REG Node = 'count[1]'
            Info: Total cell delay = 1.900 ns ( 48.72 % )
            Info: Total interconnect delay = 2.000 ns ( 51.28 % )
    Info: + Micro clock to output delay of source is 0.900 ns
    Info: + Micro setup delay of destination is 1.300 ns
Info: tsu for register "count[1]" (data pin = "setmin", clock pin = "clk") is 2.400 ns
    Info: + Longest pin to register delay is 5.000 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_44; Fanout = 8; PIN Node = 'setmin'
        Info: 2: + IC(2.100 ns) + CELL(1.000 ns) = 5.000 ns; Loc. = LC3_A15; Fanout = 5; REG Node = 'count[1]'
        Info: Total cell delay = 2.900 ns ( 58.00 % )
        Info: Total interconnect delay = 2.100 ns ( 42.00 % )
    Info: + Micro setup delay of destination is 1.300 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'clk'
        Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC3_A15; Fanout = 5; REG Node = 'count[1]'
        Info: Total cell delay = 1.900 ns ( 48.72 % )
        Info: Total interconnect delay = 2.000 ns ( 51.28 % )
Info: tco from clock "clk" to destination pin "daout[5]" through register "count[5]" is 10.900 ns
    Info: + Longest clock path from clock "clk" to source register is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'clk'
        Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_A13; Fanout = 8; REG Node = 'count[5]'
        Info: Total cell delay = 1.900 ns ( 48.72 % )
        Info: Total interconnect delay = 2.000 ns ( 51.28 % )
    Info: + Micro clock to output delay of source is 0.900 ns
    Info: + Longest register to pin delay is 6.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A13; Fanout = 8; REG Node = 'count[5]'
        Info: 2: + IC(2.200 ns) + CELL(3.900 ns) = 6.100 ns; Loc. = PIN_16; Fanout = 0; PIN Node = 'daout[5]'
        Info: Total cell delay = 3.900 ns ( 63.93 % )
        Info: Total interconnect delay = 2.200 ns ( 36.07 % )
Info: th for register "enmin~reg0" (data pin = "reset", clock pin = "clk") is 0.700 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'clk'
        Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC5_A13; Fanout = 2; REG Node = 'enmin~reg0'
        Info: Total cell delay = 1.900 ns ( 48.72 % )
        Info: Total interconnect delay = 2.000 ns ( 51.28 % )
    Info: + Micro hold delay of destination is 1.400 ns
    Info: - Shortest pin to register delay is 4.600 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_84; Fanout = 9; PIN Node = 'reset'
        Info: 2: + IC(1.700 ns) + CELL(1.000 ns) = 4.600 ns; Loc. = LC5_A13; Fanout = 2; REG Node = 'enmin~reg0'
        Info: Total cell delay = 2.900 ns ( 63.04 % )
        Info: Total interconnect delay = 1.700 ns ( 36.96 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Oct 28 16:51:46 2008
    Info: Elapsed time: 00:00:01