second.tan.qmsg

vhdl语言

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "second.vhd" "" { Text "F:/vhdlpjt/clock/second.vhd" 6 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register count\[1\] register count\[4\] 73.53 MHz 13.6 ns Internal " "Info: Clock \"clk\" has Internal fmax of 73.53 MHz between source register \"count\[1\]\" and destination register \"count\[4\]\" (period= 13.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.400 ns + Longest register register " "Info: + Longest register to register delay is 11.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[1\] 1 REG LC3_A15 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_A15; Fanout = 5; REG Node = 'count\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/second.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { count[1] } "NODE_NAME" } "" } } { "second.vhd" "" { Text "F:/vhdlpjt/clock/second.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 2.500 ns rtl~59 2 COMB LC1_A15 3 " "Info: 2: + IC(0.600 ns) + CELL(1.900 ns) = 2.500 ns; Loc. = LC1_A15; Fanout = 3; COMB Node = 'rtl~59'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/second.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "2.500 ns" { count[1] rtl~59 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.900 ns) 6.200 ns count~688 3 COMB LC2_A13 4 " "Info: 3: + IC(1.800 ns) + CELL(1.900 ns) = 6.200 ns; Loc. = LC2_A13; Fanout = 4; COMB Node = 'count~688'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/second.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.700 ns" { rtl~59 count~688 } "NODE_NAME" } "" } } { "second.vhd" "" { Text "F:/vhdlpjt/clock/second.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.900 ns) 9.900 ns count~692 4 COMB LC1_A14 1 " "Info: 4: + IC(1.800 ns) + CELL(1.900 ns) = 9.900 ns; Loc. = LC1_A14; Fanout = 1; COMB Node = 'count~692'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/second.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.700 ns" { count~688 count~692 } "NODE_NAME" } "" } } { "second.vhd" "" { Text "F:/vhdlpjt/clock/second.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.900 ns) 11.400 ns count\[4\] 5 REG LC8_A14 6 " "Info: 5: + IC(0.600 ns) + CELL(0.900 ns) = 11.400 ns; Loc. = LC8_A14; Fanout = 6; REG Node = 'count\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/second.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "1.500 ns" { count~692 count[4] } "NODE_NAME" } "" } } { "second.vhd" "" { Text "F:/vhdlpjt/clock/second.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.600 ns ( 57.89 % ) " "Info: Total cell delay = 6.600 ns ( 57.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.800 ns ( 42.11 % ) " "Info: Total interconnect delay = 4.800 ns ( 42.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/second.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "11.400 ns" { count[1] rtl~59 count~688 count~692 count[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.400 ns" { count[1] rtl~59 count~688 count~692 count[4] } { 0.000ns 0.600ns 1.800ns 1.800ns 0.600ns } { 0.000ns 1.900ns 1.900ns 1.900ns 0.900ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK PIN_43 9 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/second.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { clk } "NODE_NAME" } "" } } { "second.vhd" "" { Text "F:/vhdlpjt/clock/second.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns count\[4\] 2 REG LC8_A14 6 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC8_A14; Fanout = 6; REG Node = 'count\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/second.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "2.000 ns" { clk count[4] } "NODE_NAME" } "" } } { "second.vhd" "" { Text "F:/vhdlpjt/clock/second.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/second.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clk count[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out count[4] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.900 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK PIN_43 9 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/second.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { clk } "NODE_NAME" } "" } } { "second.vhd" "" { Text "F:/vhdlpjt/clock/second.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns count\[1\] 2 REG LC3_A15 5 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC3_A15; Fanout = 5; REG Node = 'count\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/second.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "2.000 ns" { clk count[1] } "NODE_NAME" } "" } } { "second.vhd" "" { Text "F:/vhdlpjt/clock/second.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/second.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clk count[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out count[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/second.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clk count[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out count[4] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/second.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clk count[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out count[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "second.vhd" "" { Text "F:/vhdlpjt/clock/second.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "second.vhd" "" { Text "F:/vhdlpjt/clock/second.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/second.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "11.400 ns" { count[1] rtl~59 count~688 count~692 count[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.400 ns" { count[1] rtl~59 count~688 count~692 count[4] } { 0.000ns 0.600ns 1.800ns 1.800ns 0.600ns } { 0.000ns 1.900ns 1.900ns 1.900ns 0.900ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/second.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clk count[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out count[4] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/second.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clk count[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out count[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "count\[1\] setmin clk 2.400 ns register " "Info: tsu for register \"count\[1\]\" (data pin = \"setmin\", clock pin = \"clk\") is 2.400 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.000 ns + Longest pin register " "Info: + Longest pin to register delay is 5.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns setmin 1 PIN PIN_44 8 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_44; Fanout = 8; PIN Node = 'setmin'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/second.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { setmin } "NODE_NAME" } "" } } { "second.vhd" "" { Text "F:/vhdlpjt/clock/second.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(1.000 ns) 5.000 ns count\[1\] 2 REG LC3_A15 5 " "Info: 2: + IC(2.100 ns) + CELL(1.000 ns) = 5.000 ns; Loc. = LC3_A15; Fanout = 5; REG Node = 'count\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/second.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.100 ns" { setmin count[1] } "NODE_NAME" } "" } } { "second.vhd" "" { Text "F:/vhdlpjt/clock/second.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.900 ns ( 58.00 % ) " "Info: Total cell delay = 2.900 ns ( 58.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.100 ns ( 42.00 % ) " "Info: Total interconnect delay = 2.100 ns ( 42.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/second.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "5.000 ns" { setmin count[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.000 ns" { setmin setmin~out count[1] } { 0.000ns 0.000ns 2.100ns } { 0.000ns 1.900ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "second.vhd" "" { Text "F:/vhdlpjt/clock/second.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.900 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK PIN_43 9 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/second.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { clk } "NODE_NAME" } "" } } { "second.vhd" "" { Text "F:/vhdlpjt/clock/second.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns count\[1\] 2 REG LC3_A15 5 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC3_A15; Fanout = 5; REG Node = 'count\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/second.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "2.000 ns" { clk count[1] } "NODE_NAME" } "" } } { "second.vhd" "" { Text "F:/vhdlpjt/clock/second.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/second.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clk count[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out count[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/second.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "5.000 ns" { setmin count[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.000 ns" { setmin setmin~out count[1] } { 0.000ns 0.000ns 2.100ns } { 0.000ns 1.900ns 1.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/second.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clk count[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out count[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}