clock.map.qmsg

vhdl语言

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seltime seltime:inst5 " "Info: Elaborating entity \"seltime\" for hierarchy \"seltime:inst5\"" {  } { { "clock.bdf" "inst5" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 312 752 904 440 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count seltime.vhd(28) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(28): signal \"count\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 28 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sec seltime.vhd(29) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(29): signal \"sec\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 29 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sec seltime.vhd(31) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(31): signal \"sec\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 31 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min seltime.vhd(32) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(32): signal \"min\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 32 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min seltime.vhd(34) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(34): signal \"min\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 34 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour seltime.vhd(35) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(35): signal \"hour\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 35 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour seltime.vhd(37) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(37): signal \"hour\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 37 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "hour.vhd 2 1 " "Warning: Using design file hour.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 hour-fun " "Info: Found design unit 1: hour-fun" {  } { { "hour.vhd" "" { Text "F:/vhdlpjt/clock/hour.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 hour " "Info: Found entity 1: hour" {  } { { "hour.vhd" "" { Text "F:/vhdlpjt/clock/hour.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hour hour:inst1 " "Info: Elaborating entity \"hour\" for hierarchy \"hour:inst1\"" {  } { { "clock.bdf" "inst1" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 504 424 552 600 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "deled.vhd 2 1 " "Warning: Using design file deled.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 deled-fun " "Info: Found design unit 1: deled-fun" {  } { { "deled.vhd" "" { Text "F:/vhdlpjt/clock/deled.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 deled " "Info: Found entity 1: deled" {  } { { "deled.vhd" "" { Text "F:/vhdlpjt/clock/deled.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "deled deled:inst4 " "Info: Elaborating entity \"deled\" for hierarchy \"deled:inst4\"" {  } { { "clock.bdf" "inst4" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 528 752 896 624 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "a GND " "Warning: Pin \"a\" stuck at GND" {  } { { "clock.bdf" "" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 520 1032 1208 536 "a" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "b GND " "Warning: Pin \"b\" stuck at GND" {  } { { "clock.bdf" "" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 536 1032 1208 552 "b" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "c GND " "Warning: Pin \"c\" stuck at GND" {  } { { "clock.bdf" "" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 552 1032 1208 568 "c" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "d GND " "Warning: Pin \"d\" stuck at GND" {  } { { "clock.bdf" "" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 568 1032 1208 584 "d" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "e GND " "Warning: Pin \"e\" stuck at GND" {  } { { "clock.bdf" "" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 584 1032 1208 600 "e" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "f GND " "Warning: Pin \"f\" stuck at GND" {  } { { "clock.bdf" "" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 600 1032 1208 616 "f" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "g GND " "Warning: Pin \"g\" stuck at GND" {  } { { "clock.bdf" "" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 616 1032 1208 632 "g" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "88 " "Info: Implemented 88 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "14 " "Info: Implemented 14 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "69 " "Info: Implemented 69 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 30 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 30 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 29 17:46:49 2008 " "Info: Processing ended: Wed Oct 29 17:46:49 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}