clock_top.map.qmsg

vhdl语言

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count seltime.vhd(28) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(28): signal \"count\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 28 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sec seltime.vhd(29) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(29): signal \"sec\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 29 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sec seltime.vhd(31) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(31): signal \"sec\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 31 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min seltime.vhd(32) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(32): signal \"min\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 32 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min seltime.vhd(34) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(34): signal \"min\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 34 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour seltime.vhd(35) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(35): signal \"hour\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 35 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour seltime.vhd(37) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(37): signal \"hour\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 37 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "deled.vhd 2 1 " "Warning: Using design file deled.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 deled-fun " "Info: Found design unit 1: deled-fun" {  } { { "deled.vhd" "" { Text "F:/vhdlpjt/clock/deled.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 deled " "Info: Found entity 1: deled" {  } { { "deled.vhd" "" { Text "F:/vhdlpjt/clock/deled.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "deled deled:u6 " "Info: Elaborating entity \"deled\" for hierarchy \"deled:u6\"" {  } { { "clock_top.vhd" "u6" { Text "F:/vhdlpjt/clock/clock_top.vhd" 104 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "dp GND " "Warning: Pin \"dp\" stuck at GND" {  } { { "clock_top.vhd" "" { Text "F:/vhdlpjt/clock/clock_top.vhd" 8 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "174 " "Info: Implemented 174 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "15 " "Info: Implemented 15 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "154 " "Info: Implemented 154 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 17 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Oct 27 17:07:29 2008 " "Info: Processing ended: Mon Oct 27 17:07:29 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}