clock_top.tan.qmsg

vhdl语言

{ "Info" "ITDB_TH_RESULT" "minute:u2\|enhour reset clk 6.100 ns register " "Info: th for register \"minute:u2\|enhour\" (data pin = \"reset\", clock pin = \"clk\") is 6.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 9.500 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 9.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK PIN_43 17 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 17; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock_top" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock_top.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { clk } "NODE_NAME" } "" } } { "clock_top.vhd" "" { Text "F:/vhdlpjt/clock/clock_top.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.900 ns) 4.800 ns second:u1\|enmin 2 REG LC1_B13 9 " "Info: 2: + IC(2.000 ns) + CELL(0.900 ns) = 4.800 ns; Loc. = LC1_B13; Fanout = 9; REG Node = 'second:u1\|enmin'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock_top" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock_top.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "2.900 ns" { clk second:u1|enmin } "NODE_NAME" } "" } } { "second.vhd" "" { Text "F:/vhdlpjt/clock/second.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.700 ns) + CELL(0.000 ns) 9.500 ns minute:u2\|enhour 3 REG LC6_A14 7 " "Info: 3: + IC(4.700 ns) + CELL(0.000 ns) = 9.500 ns; Loc. = LC6_A14; Fanout = 7; REG Node = 'minute:u2\|enhour'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock_top" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock_top.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "4.700 ns" { second:u1|enmin minute:u2|enhour } "NODE_NAME" } "" } } { "minute.vhd" "" { Text "F:/vhdlpjt/clock/minute.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 29.47 % ) " "Info: Total cell delay = 2.800 ns ( 29.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.700 ns ( 70.53 % ) " "Info: Total interconnect delay = 6.700 ns ( 70.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock_top" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock_top.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "9.500 ns" { clk second:u1|enmin minute:u2|enhour } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.500 ns" { clk clk~out second:u1|enmin minute:u2|enhour } { 0.000ns 0.000ns 2.000ns 4.700ns } { 0.000ns 1.900ns 0.900ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.400 ns + " "Info: + Micro hold delay of destination is 1.400 ns" {  } { { "minute.vhd" "" { Text "F:/vhdlpjt/clock/minute.vhd" 7 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.800 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns reset 1 PIN PIN_84 27 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_84; Fanout = 27; PIN Node = 'reset'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock_top" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock_top.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { reset } "NODE_NAME" } "" } } { "clock_top.vhd" "" { Text "F:/vhdlpjt/clock/clock_top.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.000 ns) 4.800 ns minute:u2\|enhour 2 REG LC6_A14 7 " "Info: 2: + IC(1.900 ns) + CELL(1.000 ns) = 4.800 ns; Loc. = LC6_A14; Fanout = 7; REG Node = 'minute:u2\|enhour'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock_top" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock_top.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "2.900 ns" { reset minute:u2|enhour } "NODE_NAME" } "" } } { "minute.vhd" "" { Text "F:/vhdlpjt/clock/minute.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.900 ns ( 60.42 % ) " "Info: Total cell delay = 2.900 ns ( 60.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.900 ns ( 39.58 % ) " "Info: Total interconnect delay = 1.900 ns ( 39.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock_top" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock_top.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "4.800 ns" { reset minute:u2|enhour } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.800 ns" { reset reset~out minute:u2|enhour } { 0.000ns 0.000ns 1.900ns } { 0.000ns 1.900ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock_top" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock_top.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "9.500 ns" { clk second:u1|enmin minute:u2|enhour } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.500 ns" { clk clk~out second:u1|enmin minute:u2|enhour } { 0.000ns 0.000ns 2.000ns 4.700ns } { 0.000ns 1.900ns 0.900ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock_top" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock_top.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "4.800 ns" { reset minute:u2|enhour } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.800 ns" { reset reset~out minute:u2|enhour } { 0.000ns 0.000ns 1.900ns } { 0.000ns 1.900ns 1.000ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 10 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Oct 27 17:07:40 2008 " "Info: Processing ended: Mon Oct 27 17:07:40 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}