clock_top.tan.qmsg

vhdl语言

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTAN_COMB_LATCH_NODE" "deled:u6\|led\[0\] " "Warning: Node \"deled:u6\|led\[0\]\" is a latch" {  } { { "deled.vhd" "" { Text "F:/vhdlpjt/clock/deled.vhd" 10 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "deled:u6\|led\[1\] " "Warning: Node \"deled:u6\|led\[1\]\" is a latch" {  } { { "deled.vhd" "" { Text "F:/vhdlpjt/clock/deled.vhd" 10 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "deled:u6\|led\[2\] " "Warning: Node \"deled:u6\|led\[2\]\" is a latch" {  } { { "deled.vhd" "" { Text "F:/vhdlpjt/clock/deled.vhd" 10 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "deled:u6\|led\[3\] " "Warning: Node \"deled:u6\|led\[3\]\" is a latch" {  } { { "deled.vhd" "" { Text "F:/vhdlpjt/clock/deled.vhd" 10 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "deled:u6\|led\[4\] " "Warning: Node \"deled:u6\|led\[4\]\" is a latch" {  } { { "deled.vhd" "" { Text "F:/vhdlpjt/clock/deled.vhd" 10 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "deled:u6\|led\[5\] " "Warning: Node \"deled:u6\|led\[5\]\" is a latch" {  } { { "deled.vhd" "" { Text "F:/vhdlpjt/clock/deled.vhd" 10 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "deled:u6\|led\[6\] " "Warning: Node \"deled:u6\|led\[6\]\" is a latch" {  } { { "deled.vhd" "" { Text "F:/vhdlpjt/clock/deled.vhd" 10 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "clock_top.vhd" "" { Text "F:/vhdlpjt/clock/clock_top.vhd" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clkdsp " "Info: Assuming node \"clkdsp\" is an undefined clock" {  } { { "clock_top.vhd" "" { Text "F:/vhdlpjt/clock/clock_top.vhd" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clkdsp" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "minute:u2\|enhour " "Info: Detected ripple clock \"minute:u2\|enhour\" as buffer" {  } { { "minute.vhd" "" { Text "F:/vhdlpjt/clock/minute.vhd" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "minute:u2\|enhour" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "second:u1\|enmin " "Info: Detected ripple clock \"second:u1\|enmin\" as buffer" {  } { { "second.vhd" "" { Text "F:/vhdlpjt/clock/second.vhd" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "second:u1\|enmin" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}