seltime.tan.qmsg

vhdl语言

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk1 register register count\[2\] count\[0\] 125.0 MHz Internal " "Info: Clock \"clk1\" Internal fmax is restricted to 125.0 MHz between source register \"count\[2\]\" and destination register \"count\[0\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "4.0 ns 4.0 ns 8.0 ns " "Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.000 ns + Longest register register " "Info: + Longest register to register delay is 2.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[2\] 1 REG LC1_A11 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A11; Fanout = 9; REG Node = 'count\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { count[2] } "NODE_NAME" } "" } } { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.400 ns) 2.000 ns count\[0\] 2 REG LC8_A11 12 " "Info: 2: + IC(0.600 ns) + CELL(1.400 ns) = 2.000 ns; Loc. = LC8_A11; Fanout = 12; REG Node = 'count\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "2.000 ns" { count[2] count[0] } "NODE_NAME" } "" } } { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.400 ns ( 70.00 % ) " "Info: Total cell delay = 1.400 ns ( 70.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns ( 30.00 % ) " "Info: Total interconnect delay = 0.600 ns ( 30.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "2.000 ns" { count[2] count[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.000 ns" { count[2] count[0] } { 0.000ns 0.600ns } { 0.000ns 1.400ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 3.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clk1\" to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk1 1 CLK PIN_43 3 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 3; CLK Node = 'clk1'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { clk1 } "NODE_NAME" } "" } } { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns count\[0\] 2 REG LC8_A11 12 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC8_A11; Fanout = 12; REG Node = 'count\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "2.000 ns" { clk1 count[0] } "NODE_NAME" } "" } } { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clk1 count[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clk1 clk1~out count[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 3.900 ns - Longest register " "Info: - Longest clock path from clock \"clk1\" to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk1 1 CLK PIN_43 3 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 3; CLK Node = 'clk1'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { clk1 } "NODE_NAME" } "" } } { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns count\[2\] 2 REG LC1_A11 9 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_A11; Fanout = 9; REG Node = 'count\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "2.000 ns" { clk1 count[2] } "NODE_NAME" } "" } } { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clk1 count[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clk1 clk1~out count[2] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clk1 count[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clk1 clk1~out count[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clk1 count[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clk1 clk1~out count[2] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "2.000 ns" { count[2] count[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.000 ns" { count[2] count[0] } { 0.000ns 0.600ns } { 0.000ns 1.400ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clk1 count[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clk1 clk1~out count[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clk1 count[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clk1 clk1~out count[2] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { count[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { count[0] } {  } {  } } } { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 19 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk1 daout\[2\] count\[1\] 20.900 ns register " "Info: tco from clock \"clk1\" to destination pin \"daout\[2\]\" through register \"count\[1\]\" is 20.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 3.900 ns + Longest register " "Info: + Longest clock path from clock \"clk1\" to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk1 1 CLK PIN_43 3 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 3; CLK Node = 'clk1'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { clk1 } "NODE_NAME" } "" } } { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns count\[1\] 2 REG LC7_A11 13 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC7_A11; Fanout = 13; REG Node = 'count\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "2.000 ns" { clk1 count[1] } "NODE_NAME" } "" } } { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clk1 count[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clk1 clk1~out count[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.100 ns + Longest register pin " "Info: + Longest register to pin delay is 16.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[1\] 1 REG LC7_A11 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_A11; Fanout = 13; REG Node = 'count\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { count[1] } "NODE_NAME" } "" } } { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.900 ns) 3.700 ns Mux~508 2 COMB LC1_A5 1 " "Info: 2: + IC(1.800 ns) + CELL(1.900 ns) = 3.700 ns; Loc. = LC1_A5; Fanout = 1; COMB Node = 'Mux~508'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.700 ns" { count[1] Mux~508 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.900 ns) 7.500 ns Mux~509 3 COMB LC5_A11 1 " "Info: 3: + IC(1.900 ns) + CELL(1.900 ns) = 7.500 ns; Loc. = LC5_A11; Fanout = 1; COMB Node = 'Mux~509'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.800 ns" { Mux~508 Mux~509 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 10.000 ns Mux~510 4 COMB LC3_A11 1 " "Info: 4: + IC(0.600 ns) + CELL(1.900 ns) = 10.000 ns; Loc. = LC3_A11; Fanout = 1; COMB Node = 'Mux~510'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "2.500 ns" { Mux~509 Mux~510 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(3.900 ns) 16.100 ns daout\[2\] 5 PIN PIN_17 0 " "Info: 5: + IC(2.200 ns) + CELL(3.900 ns) = 16.100 ns; Loc. = PIN_17; Fanout = 0; PIN Node = 'daout\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "6.100 ns" { Mux~510 daout[2] } "NODE_NAME" } "" } } { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.600 ns ( 59.63 % ) " "Info: Total cell delay = 9.600 ns ( 59.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.500 ns ( 40.37 % ) " "Info: Total interconnect delay = 6.500 ns ( 40.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "16.100 ns" { count[1] Mux~508 Mux~509 Mux~510 daout[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "16.100 ns" { count[1] Mux~508 Mux~509 Mux~510 daout[2] } { 0.000ns 1.800ns 1.900ns 0.600ns 2.200ns } { 0.000ns 1.900ns 1.900ns 1.900ns 3.900ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clk1 count[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clk1 clk1~out count[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "16.100 ns" { count[1] Mux~508 Mux~509 Mux~510 daout[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "16.100 ns" { count[1] Mux~508 Mux~509 Mux~510 daout[2] } { 0.000ns 1.800ns 1.900ns 0.600ns 2.200ns } { 0.000ns 1.900ns 1.900ns 1.900ns 3.900ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "min\[2\] daout\[2\] 20.000 ns Longest " "Info: Longest tpd from source pin \"min\[2\]\" to destination pin \"daout\[2\]\" is 20.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns min\[2\] 1 PIN PIN_8 1 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_8; Fanout = 1; PIN Node = 'min\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { min[2] } "NODE_NAME" } "" } } { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(1.900 ns) 7.600 ns Mux~508 2 COMB LC1_A5 1 " "Info: 2: + IC(2.600 ns) + CELL(1.900 ns) = 7.600 ns; Loc. = LC1_A5; Fanout = 1; COMB Node = 'Mux~508'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "4.500 ns" { min[2] Mux~508 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.900 ns) 11.400 ns Mux~509 3 COMB LC5_A11 1 " "Info: 3: + IC(1.900 ns) + CELL(1.900 ns) = 11.400 ns; Loc. = LC5_A11; Fanout = 1; COMB Node = 'Mux~509'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.800 ns" { Mux~508 Mux~509 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 13.900 ns Mux~510 4 COMB LC3_A11 1 " "Info: 4: + IC(0.600 ns) + CELL(1.900 ns) = 13.900 ns; Loc. = LC3_A11; Fanout = 1; COMB Node = 'Mux~510'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "2.500 ns" { Mux~509 Mux~510 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(3.900 ns) 20.000 ns daout\[2\] 5 PIN PIN_17 0 " "Info: 5: + IC(2.200 ns) + CELL(3.900 ns) = 20.000 ns; Loc. = PIN_17; Fanout = 0; PIN Node = 'daout\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "6.100 ns" { Mux~510 daout[2] } "NODE_NAME" } "" } } { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.700 ns ( 63.50 % ) " "Info: Total cell delay = 12.700 ns ( 63.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.300 ns ( 36.50 % ) " "Info: Total interconnect delay = 7.300 ns ( 36.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "seltime" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/seltime.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "20.000 ns" { min[2] Mux~508 Mux~509 Mux~510 daout[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "20.000 ns" { min[2] min[2]~out Mux~508 Mux~509 Mux~510 daout[2] } { 0.000ns 0.000ns 2.600ns 1.900ns 0.600ns 2.200ns } { 0.000ns 3.100ns 1.900ns 1.900ns 1.900ns 3.900ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Oct 27 16:14:23 2008 " "Info: Processing ended: Mon Oct 27 16:14:23 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}