alert.tan.qmsg

vhdl语言

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "alert.vhd" "" { Text "F:/vhdlpjt/clock/alert.vhd" 6 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register count\[1\] lamp\[2\]~reg0 125.0 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 125.0 MHz between source register \"count\[1\]\" and destination register \"lamp\[2\]~reg0\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "4.0 ns 4.0 ns 8.0 ns " "Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.100 ns + Longest register register " "Info: + Longest register to register delay is 4.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[1\] 1 REG LC3_B11 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_B11; Fanout = 5; REG Node = 'count\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/alert.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { count[1] } "NODE_NAME" } "" } } { "alert.vhd" "" { Text "F:/vhdlpjt/clock/alert.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 2.500 ns LessThan~27 2 COMB LC4_B11 3 " "Info: 2: + IC(0.600 ns) + CELL(1.900 ns) = 2.500 ns; Loc. = LC4_B11; Fanout = 3; COMB Node = 'LessThan~27'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/alert.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "2.500 ns" { count[1] LessThan~27 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.000 ns) 4.100 ns lamp\[2\]~reg0 3 REG LC6_B11 2 " "Info: 3: + IC(0.600 ns) + CELL(1.000 ns) = 4.100 ns; Loc. = LC6_B11; Fanout = 2; REG Node = 'lamp\[2\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/alert.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "1.600 ns" { LessThan~27 lamp[2]~reg0 } "NODE_NAME" } "" } } { "alert.vhd" "" { Text "F:/vhdlpjt/clock/alert.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.900 ns ( 70.73 % ) " "Info: Total cell delay = 2.900 ns ( 70.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns ( 29.27 % ) " "Info: Total interconnect delay = 1.200 ns ( 29.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/alert.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "4.100 ns" { count[1] LessThan~27 lamp[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.100 ns" { count[1] LessThan~27 lamp[2]~reg0 } { 0.000ns 0.600ns 0.600ns } { 0.000ns 1.900ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK PIN_43 7 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/alert.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { clk } "NODE_NAME" } "" } } { "alert.vhd" "" { Text "F:/vhdlpjt/clock/alert.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns lamp\[2\]~reg0 2 REG LC6_B11 2 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC6_B11; Fanout = 2; REG Node = 'lamp\[2\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/alert.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "2.000 ns" { clk lamp[2]~reg0 } "NODE_NAME" } "" } } { "alert.vhd" "" { Text "F:/vhdlpjt/clock/alert.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/alert.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clk lamp[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out lamp[2]~reg0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.900 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK PIN_43 7 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/alert.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { clk } "NODE_NAME" } "" } } { "alert.vhd" "" { Text "F:/vhdlpjt/clock/alert.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns count\[1\] 2 REG LC3_B11 5 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC3_B11; Fanout = 5; REG Node = 'count\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/alert.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "2.000 ns" { clk count[1] } "NODE_NAME" } "" } } { "alert.vhd" "" { Text "F:/vhdlpjt/clock/alert.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/alert.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clk count[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out count[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/alert.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clk lamp[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out lamp[2]~reg0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/alert.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clk count[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out count[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "alert.vhd" "" { Text "F:/vhdlpjt/clock/alert.vhd" 31 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "alert.vhd" "" { Text "F:/vhdlpjt/clock/alert.vhd" 31 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/alert.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "4.100 ns" { count[1] LessThan~27 lamp[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.100 ns" { count[1] LessThan~27 lamp[2]~reg0 } { 0.000ns 0.600ns 0.600ns } { 0.000ns 1.900ns 1.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/alert.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clk lamp[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out lamp[2]~reg0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/alert.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clk count[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out count[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/alert.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { lamp[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { lamp[2]~reg0 } {  } {  } } } { "alert.vhd" "" { Text "F:/vhdlpjt/clock/alert.vhd" 31 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "count1\[1\] dain\[6\] clk 6.700 ns register " "Info: tsu for register \"count1\[1\]\" (data pin = \"dain\[6\]\", clock pin = \"clk\") is 6.700 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.300 ns + Longest pin register " "Info: + Longest pin to register delay is 9.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns dain\[6\] 1 PIN PIN_29 1 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_29; Fanout = 1; PIN Node = 'dain\[6\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/alert.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { dain[6] } "NODE_NAME" } "" } } { "alert.vhd" "" { Text "F:/vhdlpjt/clock/alert.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(1.900 ns) 7.700 ns rtl~0 2 COMB LC4_C18 2 " "Info: 2: + IC(2.700 ns) + CELL(1.900 ns) = 7.700 ns; Loc. = LC4_C18; Fanout = 2; COMB Node = 'rtl~0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/alert.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "4.600 ns" { dain[6] rtl~0 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.000 ns) 9.300 ns count1\[1\] 3 REG LC2_C18 3 " "Info: 3: + IC(0.600 ns) + CELL(1.000 ns) = 9.300 ns; Loc. = LC2_C18; Fanout = 3; REG Node = 'count1\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/alert.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "1.600 ns" { rtl~0 count1[1] } "NODE_NAME" } "" } } { "alert.vhd" "" { Text "F:/vhdlpjt/clock/alert.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns ( 64.52 % ) " "Info: Total cell delay = 6.000 ns ( 64.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns ( 35.48 % ) " "Info: Total interconnect delay = 3.300 ns ( 35.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/alert.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "9.300 ns" { dain[6] rtl~0 count1[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.300 ns" { dain[6] dain[6]~out rtl~0 count1[1] } { 0.000ns 0.000ns 2.700ns 0.600ns } { 0.000ns 3.100ns 1.900ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "alert.vhd" "" { Text "F:/vhdlpjt/clock/alert.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.900 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK PIN_43 7 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/alert.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { clk } "NODE_NAME" } "" } } { "alert.vhd" "" { Text "F:/vhdlpjt/clock/alert.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns count1\[1\] 2 REG LC2_C18 3 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC2_C18; Fanout = 3; REG Node = 'count1\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/alert.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "2.000 ns" { clk count1[1] } "NODE_NAME" } "" } } { "alert.vhd" "" { Text "F:/vhdlpjt/clock/alert.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/alert.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clk count1[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out count1[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/alert.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "9.300 ns" { dain[6] rtl~0 count1[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.300 ns" { dain[6] dain[6]~out rtl~0 count1[1] } { 0.000ns 0.000ns 2.700ns 0.600ns } { 0.000ns 3.100ns 1.900ns 1.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/alert.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clk count1[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out count1[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}