clock.tan.qmsg

vhdl语言

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clkdsp register register seltime:inst5\|count\[0\] seltime:inst5\|count\[1\] 125.0 MHz Internal " "Info: Clock \"clkdsp\" Internal fmax is restricted to 125.0 MHz between source register \"seltime:inst5\|count\[0\]\" and destination register \"seltime:inst5\|count\[1\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "4.0 ns 4.0 ns 8.0 ns " "Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.000 ns + Longest register register " "Info: + Longest register to register delay is 2.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns seltime:inst5\|count\[0\] 1 REG LC3_C14 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_C14; Fanout = 4; REG Node = 'seltime:inst5\|count\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { seltime:inst5|count[0] } "NODE_NAME" } "" } } { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.400 ns) 2.000 ns seltime:inst5\|count\[1\] 2 REG LC1_C14 4 " "Info: 2: + IC(0.600 ns) + CELL(1.400 ns) = 2.000 ns; Loc. = LC1_C14; Fanout = 4; REG Node = 'seltime:inst5\|count\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "2.000 ns" { seltime:inst5|count[0] seltime:inst5|count[1] } "NODE_NAME" } "" } } { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.400 ns ( 70.00 % ) " "Info: Total cell delay = 1.400 ns ( 70.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns ( 30.00 % ) " "Info: Total interconnect delay = 0.600 ns ( 30.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "2.000 ns" { seltime:inst5|count[0] seltime:inst5|count[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.000 ns" { seltime:inst5|count[0] seltime:inst5|count[1] } { 0.000ns 0.600ns } { 0.000ns 1.400ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkdsp destination 3.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clkdsp\" to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clkdsp 1 CLK PIN_1 3 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_1; Fanout = 3; CLK Node = 'clkdsp'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { clkdsp } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 640 208 376 656 "clkdsp" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns seltime:inst5\|count\[1\] 2 REG LC1_C14 4 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_C14; Fanout = 4; REG Node = 'seltime:inst5\|count\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "2.000 ns" { clkdsp seltime:inst5|count[1] } "NODE_NAME" } "" } } { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clkdsp seltime:inst5|count[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clkdsp clkdsp~out seltime:inst5|count[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkdsp source 3.900 ns - Longest register " "Info: - Longest clock path from clock \"clkdsp\" to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clkdsp 1 CLK PIN_1 3 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_1; Fanout = 3; CLK Node = 'clkdsp'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { clkdsp } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 640 208 376 656 "clkdsp" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns seltime:inst5\|count\[0\] 2 REG LC3_C14 4 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC3_C14; Fanout = 4; REG Node = 'seltime:inst5\|count\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "2.000 ns" { clkdsp seltime:inst5|count[0] } "NODE_NAME" } "" } } { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clkdsp seltime:inst5|count[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clkdsp clkdsp~out seltime:inst5|count[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clkdsp seltime:inst5|count[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clkdsp clkdsp~out seltime:inst5|count[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clkdsp seltime:inst5|count[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clkdsp clkdsp~out seltime:inst5|count[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "2.000 ns" { seltime:inst5|count[0] seltime:inst5|count[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.000 ns" { seltime:inst5|count[0] seltime:inst5|count[1] } { 0.000ns 0.600ns } { 0.000ns 1.400ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clkdsp seltime:inst5|count[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clkdsp clkdsp~out seltime:inst5|count[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clkdsp seltime:inst5|count[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clkdsp clkdsp~out seltime:inst5|count[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { seltime:inst5|count[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { seltime:inst5|count[1] } {  } {  } } } { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 19 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "second:inst3\|count\[4\] setmin clk 2.200 ns register " "Info: tsu for register \"second:inst3\|count\[4\]\" (data pin = \"setmin\", clock pin = \"clk\") is 2.200 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.800 ns + Longest pin register " "Info: + Longest pin to register delay is 4.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns setmin 1 PIN PIN_44 8 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_44; Fanout = 8; PIN Node = 'setmin'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { setmin } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 200 216 384 216 "setmin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.000 ns) 4.800 ns second:inst3\|count\[4\] 2 REG LC2_A17 6 " "Info: 2: + IC(1.900 ns) + CELL(1.000 ns) = 4.800 ns; Loc. = LC2_A17; Fanout = 6; REG Node = 'second:inst3\|count\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "2.900 ns" { setmin second:inst3|count[4] } "NODE_NAME" } "" } } { "second.vhd" "" { Text "F:/vhdlpjt/clock/second.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.900 ns ( 60.42 % ) " "Info: Total cell delay = 2.900 ns ( 60.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.900 ns ( 39.58 % ) " "Info: Total interconnect delay = 1.900 ns ( 39.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "4.800 ns" { setmin second:inst3|count[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.800 ns" { setmin setmin~out second:inst3|count[4] } { 0.000ns 0.000ns 1.900ns } { 0.000ns 1.900ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "second.vhd" "" { Text "F:/vhdlpjt/clock/second.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.900 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK PIN_43 16 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { clk } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 168 216 384 184 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns second:inst3\|count\[4\] 2 REG LC2_A17 6 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC2_A17; Fanout = 6; REG Node = 'second:inst3\|count\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "2.000 ns" { clk second:inst3|count[4] } "NODE_NAME" } "" } } { "second.vhd" "" { Text "F:/vhdlpjt/clock/second.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clk second:inst3|count[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out second:inst3|count[4] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "4.800 ns" { setmin second:inst3|count[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.800 ns" { setmin setmin~out second:inst3|count[4] } { 0.000ns 0.000ns 1.900ns } { 0.000ns 1.900ns 1.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clk second:inst3|count[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out second:inst3|count[4] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clkdsp sel\[0\] seltime:inst5\|count\[0\] 10.000 ns register " "Info: tco from clock \"clkdsp\" to destination pin \"sel\[0\]\" through register \"seltime:inst5\|count\[0\]\" is 10.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkdsp source 3.900 ns + Longest register " "Info: + Longest clock path from clock \"clkdsp\" to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clkdsp 1 CLK PIN_1 3 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_1; Fanout = 3; CLK Node = 'clkdsp'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { clkdsp } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 640 208 376 656 "clkdsp" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns seltime:inst5\|count\[0\] 2 REG LC3_C14 4 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC3_C14; Fanout = 4; REG Node = 'seltime:inst5\|count\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "2.000 ns" { clkdsp seltime:inst5|count[0] } "NODE_NAME" } "" } } { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clkdsp seltime:inst5|count[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clkdsp clkdsp~out seltime:inst5|count[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.200 ns + Longest register pin " "Info: + Longest register to pin delay is 5.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns seltime:inst5\|count\[0\] 1 REG LC3_C14 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_C14; Fanout = 4; REG Node = 'seltime:inst5\|count\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { seltime:inst5|count[0] } "NODE_NAME" } "" } } { "seltime.vhd" "" { Text "F:/vhdlpjt/clock/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(3.900 ns) 5.200 ns sel\[0\] 2 PIN PIN_60 0 " "Info: 2: + IC(1.300 ns) + CELL(3.900 ns) = 5.200 ns; Loc. = PIN_60; Fanout = 0; PIN Node = 'sel\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "5.200 ns" { seltime:inst5|count[0] sel[0] } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 352 960 1136 368 "sel\[2..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns ( 75.00 % ) " "Info: Total cell delay = 3.900 ns ( 75.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 25.00 % ) " "Info: Total interconnect delay = 1.300 ns ( 25.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "5.200 ns" { seltime:inst5|count[0] sel[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.200 ns" { seltime:inst5|count[0] sel[0] } { 0.000ns 1.300ns } { 0.000ns 3.900ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clkdsp seltime:inst5|count[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clkdsp clkdsp~out seltime:inst5|count[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "5.200 ns" { seltime:inst5|count[0] sel[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.200 ns" { seltime:inst5|count[0] sel[0] } { 0.000ns 1.300ns } { 0.000ns 3.900ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "minute:inst2\|count\[3\] sethour clk 5.200 ns register " "Info: th for register \"minute:inst2\|count\[3\]\" (data pin = \"sethour\", clock pin = \"clk\") is 5.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.800 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK PIN_43 16 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { clk } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 168 216 384 184 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.900 ns) 4.800 ns second:inst3\|enmin 2 REG LC1_A19 8 " "Info: 2: + IC(2.000 ns) + CELL(0.900 ns) = 4.800 ns; Loc. = LC1_A19; Fanout = 8; REG Node = 'second:inst3\|enmin'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "2.900 ns" { clk second:inst3|enmin } "NODE_NAME" } "" } } { "second.vhd" "" { Text "F:/vhdlpjt/clock/second.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.000 ns) + CELL(0.000 ns) 8.800 ns minute:inst2\|count\[3\] 3 REG LC1_A13 5 " "Info: 3: + IC(4.000 ns) + CELL(0.000 ns) = 8.800 ns; Loc. = LC1_A13; Fanout = 5; REG Node = 'minute:inst2\|count\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "4.000 ns" { second:inst3|enmin minute:inst2|count[3] } "NODE_NAME" } "" } } { "minute.vhd" "" { Text "F:/vhdlpjt/clock/minute.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 31.82 % ) " "Info: Total cell delay = 2.800 ns ( 31.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.000 ns ( 68.18 % ) " "Info: Total interconnect delay = 6.000 ns ( 68.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "8.800 ns" { clk second:inst3|enmin minute:inst2|count[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.800 ns" { clk clk~out second:inst3|enmin minute:inst2|count[3] } { 0.000ns 0.000ns 2.000ns 4.000ns } { 0.000ns 1.900ns 0.900ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.400 ns + " "Info: + Micro hold delay of destination is 1.400 ns" {  } { { "minute.vhd" "" { Text "F:/vhdlpjt/clock/minute.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns sethour 1 PIN PIN_42 7 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_42; Fanout = 7; PIN Node = 'sethour'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { sethour } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 368 208 376 384 "sethour" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(1.000 ns) 5.000 ns minute:inst2\|count\[3\] 2 REG LC1_A13 5 " "Info: 2: + IC(2.100 ns) + CELL(1.000 ns) = 5.000 ns; Loc. = LC1_A13; Fanout = 5; REG Node = 'minute:inst2\|count\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.100 ns" { sethour minute:inst2|count[3] } "NODE_NAME" } "" } } { "minute.vhd" "" { Text "F:/vhdlpjt/clock/minute.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.900 ns ( 58.00 % ) " "Info: Total cell delay = 2.900 ns ( 58.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.100 ns ( 42.00 % ) " "Info: Total interconnect delay = 2.100 ns ( 42.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "5.000 ns" { sethour minute:inst2|count[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.000 ns" { sethour sethour~out minute:inst2|count[3] } { 0.000ns 0.000ns 2.100ns } { 0.000ns 1.900ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "8.800 ns" { clk second:inst3|enmin minute:inst2|count[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.800 ns" { clk clk~out second:inst3|enmin minute:inst2|count[3] } { 0.000ns 0.000ns 2.000ns 4.000ns } { 0.000ns 1.900ns 0.900ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "5.000 ns" { sethour minute:inst2|count[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.000 ns" { sethour sethour~out minute:inst2|count[3] } { 0.000ns 0.000ns 2.100ns } { 0.000ns 1.900ns 1.000ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}