clock.tan.qmsg

vhdl语言

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "clock.bdf" "" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 168 216 384 184 "clk" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clkdsp " "Info: Assuming node \"clkdsp\" is an undefined clock" {  } { { "clock.bdf" "" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 640 208 376 656 "clkdsp" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clkdsp" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "second:inst3\|enmin " "Info: Detected ripple clock \"second:inst3\|enmin\" as buffer" {  } { { "second.vhd" "" { Text "F:/vhdlpjt/clock/second.vhd" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "second:inst3\|enmin" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register minute:inst2\|count\[5\] register alert:inst\|count1\[0\] 66.23 MHz 15.1 ns Internal " "Info: Clock \"clk\" has Internal fmax of 66.23 MHz between source register \"minute:inst2\|count\[5\]\" and destination register \"alert:inst\|count1\[0\]\" (period= 15.1 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns minute:inst2\|count\[5\] 1 REG LC4_A13 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_A13; Fanout = 8; REG Node = 'minute:inst2\|count\[5\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { minute:inst2|count[5] } "NODE_NAME" } "" } } { "minute.vhd" "" { Text "F:/vhdlpjt/clock/minute.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(1.900 ns) 3.900 ns rtl~144 2 COMB LC4_A14 1 " "Info: 2: + IC(2.000 ns) + CELL(1.900 ns) = 3.900 ns; Loc. = LC4_A14; Fanout = 1; COMB Node = 'rtl~144'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { minute:inst2|count[5] rtl~144 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 6.400 ns rtl~0 3 COMB LC7_A14 2 " "Info: 3: + IC(0.600 ns) + CELL(1.900 ns) = 6.400 ns; Loc. = LC7_A14; Fanout = 2; COMB Node = 'rtl~0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "2.500 ns" { rtl~144 rtl~0 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.000 ns) 8.000 ns alert:inst\|count1\[0\] 4 REG LC3_A14 2 " "Info: 4: + IC(0.600 ns) + CELL(1.000 ns) = 8.000 ns; Loc. = LC3_A14; Fanout = 2; REG Node = 'alert:inst\|count1\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "1.600 ns" { rtl~0 alert:inst|count1[0] } "NODE_NAME" } "" } } { "alert.vhd" "" { Text "F:/vhdlpjt/clock/alert.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.800 ns ( 60.00 % ) " "Info: Total cell delay = 4.800 ns ( 60.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.200 ns ( 40.00 % ) " "Info: Total interconnect delay = 3.200 ns ( 40.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "8.000 ns" { minute:inst2|count[5] rtl~144 rtl~0 alert:inst|count1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.000 ns" { minute:inst2|count[5] rtl~144 rtl~0 alert:inst|count1[0] } { 0.000ns 2.000ns 0.600ns 0.600ns } { 0.000ns 1.900ns 1.900ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.900 ns - Smallest " "Info: - Smallest clock skew is -4.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK PIN_43 16 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { clk } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 168 216 384 184 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns alert:inst\|count1\[0\] 2 REG LC3_A14 2 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC3_A14; Fanout = 2; REG Node = 'alert:inst\|count1\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "2.000 ns" { clk alert:inst|count1[0] } "NODE_NAME" } "" } } { "alert.vhd" "" { Text "F:/vhdlpjt/clock/alert.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clk alert:inst|count1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out alert:inst|count1[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.800 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK PIN_43 16 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "" { clk } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "F:/vhdlpjt/clock/clock.bdf" { { 168 216 384 184 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.900 ns) 4.800 ns second:inst3\|enmin 2 REG LC1_A19 8 " "Info: 2: + IC(2.000 ns) + CELL(0.900 ns) = 4.800 ns; Loc. = LC1_A19; Fanout = 8; REG Node = 'second:inst3\|enmin'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "2.900 ns" { clk second:inst3|enmin } "NODE_NAME" } "" } } { "second.vhd" "" { Text "F:/vhdlpjt/clock/second.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.000 ns) + CELL(0.000 ns) 8.800 ns minute:inst2\|count\[5\] 3 REG LC4_A13 8 " "Info: 3: + IC(4.000 ns) + CELL(0.000 ns) = 8.800 ns; Loc. = LC4_A13; Fanout = 8; REG Node = 'minute:inst2\|count\[5\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "4.000 ns" { second:inst3|enmin minute:inst2|count[5] } "NODE_NAME" } "" } } { "minute.vhd" "" { Text "F:/vhdlpjt/clock/minute.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 31.82 % ) " "Info: Total cell delay = 2.800 ns ( 31.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.000 ns ( 68.18 % ) " "Info: Total interconnect delay = 6.000 ns ( 68.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "8.800 ns" { clk second:inst3|enmin minute:inst2|count[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.800 ns" { clk clk~out second:inst3|enmin minute:inst2|count[5] } { 0.000ns 0.000ns 2.000ns 4.000ns } { 0.000ns 1.900ns 0.900ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clk alert:inst|count1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out alert:inst|count1[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "8.800 ns" { clk second:inst3|enmin minute:inst2|count[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.800 ns" { clk clk~out second:inst3|enmin minute:inst2|count[5] } { 0.000ns 0.000ns 2.000ns 4.000ns } { 0.000ns 1.900ns 0.900ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "minute.vhd" "" { Text "F:/vhdlpjt/clock/minute.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "alert.vhd" "" { Text "F:/vhdlpjt/clock/alert.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "8.000 ns" { minute:inst2|count[5] rtl~144 rtl~0 alert:inst|count1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.000 ns" { minute:inst2|count[5] rtl~144 rtl~0 alert:inst|count1[0] } { 0.000ns 2.000ns 0.600ns 0.600ns } { 0.000ns 1.900ns 1.900ns 1.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "3.900 ns" { clk alert:inst|count1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out alert:inst|count1[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/vhdlpjt/clock/db/clock.quartus_db" { Floorplan "F:/vhdlpjt/clock/" "" "8.800 ns" { clk second:inst3|enmin minute:inst2|count[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.800 ns" { clk clk~out second:inst3|enmin minute:inst2|count[5] } { 0.000ns 0.000ns 2.000ns 4.000ns } { 0.000ns 1.900ns 0.900ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}