second.hier_info

vhdl语言

|second
clk => count[5].CLK
clk => count[4].CLK
clk => count[3].CLK
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
clk => comb~0.IN0
clk => count[6].CLK
clk => enmin~reg0.CLK
clk => comb~1.IN0
reset => enmin~4.IN0
reset => count[5].ACLR
reset => count[4].ACLR
reset => count[3].ACLR
reset => count[2].ACLR
reset => count[1].ACLR
reset => count[0].ACLR
reset => count[6].ACLR
reset => enmin~reg0.ENA
setmin => enmin~4.IN1
setmin => count[5].ENA
setmin => count[4].ENA
setmin => count[3].ENA
setmin => count[2].ENA
setmin => count[1].ENA
setmin => count[0].ENA
setmin => count[6].ENA
enmin <= enmin~reg0.DB_MAX_OUTPUT_PORT_TYPE
daout[0] <= count[0].DB_MAX_OUTPUT_PORT_TYPE
daout[1] <= count[1].DB_MAX_OUTPUT_PORT_TYPE
daout[2] <= count[2].DB_MAX_OUTPUT_PORT_TYPE
daout[3] <= count[3].DB_MAX_OUTPUT_PORT_TYPE
daout[4] <= count[4].DB_MAX_OUTPUT_PORT_TYPE
daout[5] <= count[5].DB_MAX_OUTPUT_PORT_TYPE
daout[6] <= count[6].DB_MAX_OUTPUT_PORT_TYPE