seltime.tan.rpt

vhdl语言

; N/A   ; None         ; 20.900 ns  ; count[0] ; daout[2] ; clk1       ;
; N/A   ; None         ; 19.400 ns  ; count[1] ; daout[1] ; clk1       ;
; N/A   ; None         ; 19.400 ns  ; count[0] ; daout[1] ; clk1       ;
; N/A   ; None         ; 19.400 ns  ; count[1] ; daout[0] ; clk1       ;
; N/A   ; None         ; 19.400 ns  ; count[0] ; daout[0] ; clk1       ;
; N/A   ; None         ; 15.900 ns  ; count[1] ; daout[3] ; clk1       ;
; N/A   ; None         ; 15.900 ns  ; count[2] ; daout[3] ; clk1       ;
; N/A   ; None         ; 15.900 ns  ; count[2] ; daout[2] ; clk1       ;
; N/A   ; None         ; 15.400 ns  ; count[0] ; daout[3] ; clk1       ;
; N/A   ; None         ; 13.800 ns  ; count[2] ; daout[1] ; clk1       ;
; N/A   ; None         ; 13.800 ns  ; count[2] ; daout[0] ; clk1       ;
; N/A   ; None         ; 10.800 ns  ; count[1] ; sel[1]   ; clk1       ;
; N/A   ; None         ; 9.600 ns   ; count[2] ; sel[2]   ; clk1       ;
; N/A   ; None         ; 9.400 ns   ; count[0] ; sel[0]   ; clk1       ;
+-------+--------------+------------+----------+----------+------------+


+------------------------------------------------------------------+
; tpd                                                              ;
+-------+-------------------+-----------------+---------+----------+
; Slack ; Required P2P Time ; Actual P2P Time ; From    ; To       ;
+-------+-------------------+-----------------+---------+----------+
; N/A   ; None              ; 20.000 ns       ; min[2]  ; daout[2] ;
; N/A   ; None              ; 19.600 ns       ; sec[2]  ; daout[2] ;
; N/A   ; None              ; 18.000 ns       ; sec[5]  ; daout[1] ;
; N/A   ; None              ; 17.300 ns       ; sec[1]  ; daout[1] ;
; N/A   ; None              ; 17.000 ns       ; sec[0]  ; daout[0] ;
; N/A   ; None              ; 16.200 ns       ; min[3]  ; daout[3] ;
; N/A   ; None              ; 16.100 ns       ; sec[3]  ; daout[3] ;
; N/A   ; None              ; 16.100 ns       ; sec[6]  ; daout[2] ;
; N/A   ; None              ; 15.600 ns       ; min[6]  ; daout[2] ;
; N/A   ; None              ; 15.500 ns       ; sec[4]  ; daout[0] ;
; N/A   ; None              ; 15.300 ns       ; hour[1] ; daout[1] ;
; N/A   ; None              ; 15.000 ns       ; hour[5] ; daout[1] ;
; N/A   ; None              ; 15.000 ns       ; min[1]  ; daout[1] ;
; N/A   ; None              ; 14.800 ns       ; min[5]  ; daout[1] ;
; N/A   ; None              ; 14.800 ns       ; min[4]  ; daout[0] ;
; N/A   ; None              ; 13.700 ns       ; hour[3] ; daout[3] ;
; N/A   ; None              ; 13.700 ns       ; hour[2] ; daout[2] ;
; N/A   ; None              ; 13.000 ns       ; hour[4] ; daout[0] ;
; N/A   ; None              ; 13.000 ns       ; hour[0] ; daout[0] ;
; N/A   ; None              ; 13.000 ns       ; min[0]  ; daout[0] ;
+-------+-------------------+-----------------+---------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Mon Oct 27 16:14:22 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off seltime -c seltime
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk1" is an undefined clock
Info: Clock "clk1" Internal fmax is restricted to 125.0 MHz between source register "count[2]" and destination register "count[0]"
    Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.000 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A11; Fanout = 9; REG Node = 'count[2]'
            Info: 2: + IC(0.600 ns) + CELL(1.400 ns) = 2.000 ns; Loc. = LC8_A11; Fanout = 12; REG Node = 'count[0]'
            Info: Total cell delay = 1.400 ns ( 70.00 % )
            Info: Total interconnect delay = 0.600 ns ( 30.00 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk1" to destination register is 3.900 ns
                Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 3; CLK Node = 'clk1'
                Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC8_A11; Fanout = 12; REG Node = 'count[0]'
                Info: Total cell delay = 1.900 ns ( 48.72 % )
                Info: Total interconnect delay = 2.000 ns ( 51.28 % )
            Info: - Longest clock path from clock "clk1" to source register is 3.900 ns
                Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 3; CLK Node = 'clk1'
                Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_A11; Fanout = 9; REG Node = 'count[2]'
                Info: Total cell delay = 1.900 ns ( 48.72 % )
                Info: Total interconnect delay = 2.000 ns ( 51.28 % )
        Info: + Micro clock to output delay of source is 0.900 ns
        Info: + Micro setup delay of destination is 1.300 ns
Info: tco from clock "clk1" to destination pin "daout[2]" through register "count[1]" is 20.900 ns
    Info: + Longest clock path from clock "clk1" to source register is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 3; CLK Node = 'clk1'
        Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC7_A11; Fanout = 13; REG Node = 'count[1]'
        Info: Total cell delay = 1.900 ns ( 48.72 % )
        Info: Total interconnect delay = 2.000 ns ( 51.28 % )
    Info: + Micro clock to output delay of source is 0.900 ns
    Info: + Longest register to pin delay is 16.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_A11; Fanout = 13; REG Node = 'count[1]'
        Info: 2: + IC(1.800 ns) + CELL(1.900 ns) = 3.700 ns; Loc. = LC1_A5; Fanout = 1; COMB Node = 'Mux~508'
        Info: 3: + IC(1.900 ns) + CELL(1.900 ns) = 7.500 ns; Loc. = LC5_A11; Fanout = 1; COMB Node = 'Mux~509'
        Info: 4: + IC(0.600 ns) + CELL(1.900 ns) = 10.000 ns; Loc. = LC3_A11; Fanout = 1; COMB Node = 'Mux~510'
        Info: 5: + IC(2.200 ns) + CELL(3.900 ns) = 16.100 ns; Loc. = PIN_17; Fanout = 0; PIN Node = 'daout[2]'
        Info: Total cell delay = 9.600 ns ( 59.63 % )
        Info: Total interconnect delay = 6.500 ns ( 40.37 % )
Info: Longest tpd from source pin "min[2]" to destination pin "daout[2]" is 20.000 ns
    Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_8; Fanout = 1; PIN Node = 'min[2]'
    Info: 2: + IC(2.600 ns) + CELL(1.900 ns) = 7.600 ns; Loc. = LC1_A5; Fanout = 1; COMB Node = 'Mux~508'
    Info: 3: + IC(1.900 ns) + CELL(1.900 ns) = 11.400 ns; Loc. = LC5_A11; Fanout = 1; COMB Node = 'Mux~509'
    Info: 4: + IC(0.600 ns) + CELL(1.900 ns) = 13.900 ns; Loc. = LC3_A11; Fanout = 1; COMB Node = 'Mux~510'
    Info: 5: + IC(2.200 ns) + CELL(3.900 ns) = 20.000 ns; Loc. = PIN_17; Fanout = 0; PIN Node = 'daout[2]'
    Info: Total cell delay = 12.700 ns ( 63.50 % )
    Info: Total interconnect delay = 7.300 ns ( 36.50 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Oct 27 16:14:23 2008
    Info: Elapsed time: 00:00:02