hour.vhd

vhdl语言

LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY hour IS
	PORT(
		clk,reset: IN	STD_LOGIC;
		daout: out std_logic_vector (5 downto 0));
END entity hour;
ARCHITECTURE fun OF hour IS
	SIGNAL count: STD_LOGIC_VECTOR( 5 downto 0);
BEGIN
    daout <= count;
  process ( clk,reset) 
   begin 
     if (reset='0') then
          count <= "000000";
     elsif (clk' event and clk='1') then
           if (count(3 downto 0)="1001") then
               if (count <16#24#) then
                   count<=count + 7; 
               else 
                   count<="000000";
               end if;
            elsif(count <16#24#) then 
               count <= count + 1;
            else 
            	count<="000000";
            end if;
     end if;
     end process;
END fun;