alert.tan.rpt

vhdl语言

; N/A   ; None         ; 6.400 ns   ; dain[0] ; count1[0] ; clk      ;
; N/A   ; None         ; 6.400 ns   ; dain[2] ; count1[1] ; clk      ;
; N/A   ; None         ; 6.400 ns   ; dain[2] ; count1[0] ; clk      ;
; N/A   ; None         ; 5.900 ns   ; dain[4] ; count1[1] ; clk      ;
; N/A   ; None         ; 5.900 ns   ; dain[4] ; count1[0] ; clk      ;
; N/A   ; None         ; 4.400 ns   ; dain[1] ; count1[1] ; clk      ;
; N/A   ; None         ; 4.400 ns   ; dain[1] ; count1[0] ; clk      ;
+-------+--------------+------------+---------+-----------+----------+


+-------------------------------------------------------------------------+
; tco                                                                     ;
+-------+--------------+------------+--------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To      ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 10.900 ns  ; lamp[2]~reg0 ; lamp[2] ; clk        ;
; N/A   ; None         ; 10.000 ns  ; lamp[1]~reg0 ; lamp[1] ; clk        ;
; N/A   ; None         ; 10.000 ns  ; lamp[0]~reg0 ; lamp[0] ; clk        ;
; N/A   ; None         ; 9.900 ns   ; count1[1]    ; speak   ; clk        ;
+-------+--------------+------------+--------------+---------+------------+


+--------------------------------------------------------------------------+
; th                                                                       ;
+---------------+-------------+-----------+---------+-----------+----------+
; Minimum Slack ; Required th ; Actual th ; From    ; To        ; To Clock ;
+---------------+-------------+-----------+---------+-----------+----------+
; N/A           ; None        ; -1.700 ns ; dain[1] ; count1[1] ; clk      ;
; N/A           ; None        ; -1.700 ns ; dain[1] ; count1[0] ; clk      ;
; N/A           ; None        ; -3.200 ns ; dain[4] ; count1[1] ; clk      ;
; N/A           ; None        ; -3.200 ns ; dain[4] ; count1[0] ; clk      ;
; N/A           ; None        ; -3.700 ns ; dain[3] ; count1[1] ; clk      ;
; N/A           ; None        ; -3.700 ns ; dain[3] ; count1[0] ; clk      ;
; N/A           ; None        ; -3.700 ns ; dain[5] ; count1[1] ; clk      ;
; N/A           ; None        ; -3.700 ns ; dain[5] ; count1[0] ; clk      ;
; N/A           ; None        ; -3.700 ns ; dain[0] ; count1[1] ; clk      ;
; N/A           ; None        ; -3.700 ns ; dain[0] ; count1[0] ; clk      ;
; N/A           ; None        ; -3.700 ns ; dain[2] ; count1[1] ; clk      ;
; N/A           ; None        ; -3.700 ns ; dain[2] ; count1[0] ; clk      ;
; N/A           ; None        ; -4.000 ns ; dain[6] ; count1[1] ; clk      ;
; N/A           ; None        ; -4.000 ns ; dain[6] ; count1[0] ; clk      ;
+---------------+-------------+-----------+---------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Mon Oct 27 16:09:51 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off alert -c alert
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 125.0 MHz between source register "count[1]" and destination register "lamp[2]~reg0"
    Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 4.100 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_B11; Fanout = 5; REG Node = 'count[1]'
            Info: 2: + IC(0.600 ns) + CELL(1.900 ns) = 2.500 ns; Loc. = LC4_B11; Fanout = 3; COMB Node = 'LessThan~27'
            Info: 3: + IC(0.600 ns) + CELL(1.000 ns) = 4.100 ns; Loc. = LC6_B11; Fanout = 2; REG Node = 'lamp[2]~reg0'
            Info: Total cell delay = 2.900 ns ( 70.73 % )
            Info: Total interconnect delay = 1.200 ns ( 29.27 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 3.900 ns
                Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'clk'
                Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC6_B11; Fanout = 2; REG Node = 'lamp[2]~reg0'
                Info: Total cell delay = 1.900 ns ( 48.72 % )
                Info: Total interconnect delay = 2.000 ns ( 51.28 % )
            Info: - Longest clock path from clock "clk" to source register is 3.900 ns
                Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'clk'
                Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC3_B11; Fanout = 5; REG Node = 'count[1]'
                Info: Total cell delay = 1.900 ns ( 48.72 % )
                Info: Total interconnect delay = 2.000 ns ( 51.28 % )
        Info: + Micro clock to output delay of source is 0.900 ns
        Info: + Micro setup delay of destination is 1.300 ns
Info: tsu for register "count1[1]" (data pin = "dain[6]", clock pin = "clk") is 6.700 ns
    Info: + Longest pin to register delay is 9.300 ns
        Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_29; Fanout = 1; PIN Node = 'dain[6]'
        Info: 2: + IC(2.700 ns) + CELL(1.900 ns) = 7.700 ns; Loc. = LC4_C18; Fanout = 2; COMB Node = 'rtl~0'
        Info: 3: + IC(0.600 ns) + CELL(1.000 ns) = 9.300 ns; Loc. = LC2_C18; Fanout = 3; REG Node = 'count1[1]'
        Info: Total cell delay = 6.000 ns ( 64.52 % )
        Info: Total interconnect delay = 3.300 ns ( 35.48 % )
    Info: + Micro setup delay of destination is 1.300 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'clk'
        Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC2_C18; Fanout = 3; REG Node = 'count1[1]'
        Info: Total cell delay = 1.900 ns ( 48.72 % )
        Info: Total interconnect delay = 2.000 ns ( 51.28 % )
Info: tco from clock "clk" to destination pin "lamp[2]" through register "lamp[2]~reg0" is 10.900 ns
    Info: + Longest clock path from clock "clk" to source register is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'clk'
        Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC6_B11; Fanout = 2; REG Node = 'lamp[2]~reg0'
        Info: Total cell delay = 1.900 ns ( 48.72 % )
        Info: Total interconnect delay = 2.000 ns ( 51.28 % )
    Info: + Micro clock to output delay of source is 0.900 ns
    Info: + Longest register to pin delay is 6.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_B11; Fanout = 2; REG Node = 'lamp[2]~reg0'
        Info: 2: + IC(2.200 ns) + CELL(3.900 ns) = 6.100 ns; Loc. = PIN_24; Fanout = 0; PIN Node = 'lamp[2]'
        Info: Total cell delay = 3.900 ns ( 63.93 % )
        Info: Total interconnect delay = 2.200 ns ( 36.07 % )
Info: th for register "count1[1]" (data pin = "dain[1]", clock pin = "clk") is -1.700 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'clk'
        Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC2_C18; Fanout = 3; REG Node = 'count1[1]'
        Info: Total cell delay = 1.900 ns ( 48.72 % )
        Info: Total interconnect delay = 2.000 ns ( 51.28 % )
    Info: + Micro hold delay of destination is 1.400 ns
    Info: - Shortest pin to register delay is 7.000 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_1; Fanout = 1; PIN Node = 'dain[1]'
        Info: 2: + IC(1.600 ns) + CELL(1.900 ns) = 5.400 ns; Loc. = LC4_C18; Fanout = 2; COMB Node = 'rtl~0'
        Info: 3: + IC(0.600 ns) + CELL(1.000 ns) = 7.000 ns; Loc. = LC2_C18; Fanout = 3; REG Node = 'count1[1]'
        Info: Total cell delay = 4.800 ns ( 68.57 % )
        Info: Total interconnect delay = 2.200 ns ( 31.43 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Oct 27 16:09:52 2008
    Info: Elapsed time: 00:00:02