alert.map.eqn

vhdl语言

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
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-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--count1[1] is count1[1]
--operation mode is normal

count1[1]_lut_out = count1[0] & !count1[1];
count1[1] = DFFEA(count1[1]_lut_out, clk, , , A1L32, , );

--A1L7Q is count1[1]~27
--operation mode is normal

A1L7Q = count1[1];


--A1L23Q is lamp[0]~reg0
--operation mode is normal

A1L23Q_lut_out = count[0] & count[1] & A1L23Q # !count[0] & !count[1];
A1L23Q = DFFEA(A1L23Q_lut_out, clk, , , A1L30, , );

--A1L22Q is lamp[0]~122
--operation mode is normal

A1L22Q = A1L23Q;


--A1L26Q is lamp[1]~reg0
--operation mode is normal

A1L26Q_lut_out = count[0] & (A1L26Q # !count[1]);
A1L26Q = DFFEA(A1L26Q_lut_out, clk, , , A1L30, , );

--A1L25Q is lamp[1]~123
--operation mode is normal

A1L25Q = A1L26Q;


--A1L29Q is lamp[2]~reg0
--operation mode is normal

A1L29Q_lut_out = count[1] & (A1L29Q # !count[0]);
A1L29Q = DFFEA(A1L29Q_lut_out, clk, , , A1L30, , );

--A1L28Q is lamp[2]~124
--operation mode is normal

A1L28Q = A1L29Q;


--count1[0] is count1[0]
--operation mode is normal

count1[0]_lut_out = !count1[0] & !count1[1];
count1[0] = DFFEA(count1[0]_lut_out, clk, , , A1L32, , );

--A1L5Q is count1[0]~28
--operation mode is normal

A1L5Q = count1[0];


--A1L33 is rtl~42
--operation mode is normal

A1L33 = !dain[4] & !dain[3] & !dain[5] & !dain[0];

--A1L34 is rtl~43
--operation mode is normal

A1L34 = !dain[4] & !dain[3] & !dain[5] & !dain[0];


--A1L32 is rtl~0
--operation mode is normal

A1L32 = A1L33 & !dain[1] & !dain[6] & !dain[2];

--A1L35 is rtl~44
--operation mode is normal

A1L35 = A1L33 & !dain[1] & !dain[6] & !dain[2];


--count[0] is count[0]
--operation mode is normal

count[0]_lut_out = !count[0];
count[0] = DFFEA(count[0]_lut_out, clk, , , , , );

--A1L9Q is count[0]~13
--operation mode is normal

A1L9Q = count[0];


--count[1] is count[1]
--operation mode is normal

count[1]_lut_out = count[0] $ count[1];
count[1] = DFFEA(count[1]_lut_out, clk, , , , , );

--A1L11Q is count[1]~14
--operation mode is normal

A1L11Q = count[1];


--A1L30 is LessThan~27
--operation mode is normal

A1L30 = !count[1] # !count[0];

--A1L31 is LessThan~28
--operation mode is normal

A1L31 = !count[1] # !count[0];


--clk is clk
--operation mode is input

clk = INPUT();


--dain[4] is dain[4]
--operation mode is input

dain[4] = INPUT();


--dain[3] is dain[3]
--operation mode is input

dain[3] = INPUT();


--dain[5] is dain[5]
--operation mode is input

dain[5] = INPUT();


--dain[0] is dain[0]
--operation mode is input

dain[0] = INPUT();


--dain[1] is dain[1]
--operation mode is input

dain[1] = INPUT();


--dain[6] is dain[6]
--operation mode is input

dain[6] = INPUT();


--dain[2] is dain[2]
--operation mode is input

dain[2] = INPUT();


--speak is speak
--operation mode is output

speak = OUTPUT(count1[1]);


--lamp[0] is lamp[0]
--operation mode is output

lamp[0] = OUTPUT(A1L23Q);


--lamp[1] is lamp[1]
--operation mode is output

lamp[1] = OUTPUT(A1L26Q);


--lamp[2] is lamp[2]
--operation mode is output

lamp[2] = OUTPUT(A1L29Q);