clock.map.rpt

vhdl语言

; MAXIMIZE_SPEED         ; 5           ; Untyped                                      ;
; REGISTERED_AT_END      ; 0           ; Untyped                                      ;
; OPTIMIZE_FOR_SPEED     ; 1           ; Untyped                                      ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                      ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                      ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                           ;
; DEVICE_FAMILY          ; FLEX10K     ; Untyped                                      ;
; USE_WYS                ; OFF         ; Untyped                                      ;
; STYLE                  ; FAST        ; Untyped                                      ;
; CBXI_PARAMETER         ; add_sub_enh ; Untyped                                      ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                   ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                 ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                 ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                               ;
+------------------------+-------------+----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: second:inst3|lpm_add_sub:add_rtl_3 ;
+------------------------+-------------+----------------------------------------------+
; Parameter Name         ; Value       ; Type                                         ;
+------------------------+-------------+----------------------------------------------+
; LPM_WIDTH              ; 7           ; Untyped                                      ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                                      ;
; LPM_DIRECTION          ; ADD         ; Untyped                                      ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                                      ;
; LPM_PIPELINE           ; 0           ; Untyped                                      ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                      ;
; REGISTERED_AT_END      ; 0           ; Untyped                                      ;
; OPTIMIZE_FOR_SPEED     ; 1           ; Untyped                                      ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                      ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                      ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                           ;
; DEVICE_FAMILY          ; FLEX10K     ; Untyped                                      ;
; USE_WYS                ; OFF         ; Untyped                                      ;
; STYLE                  ; FAST        ; Untyped                                      ;
; CBXI_PARAMETER         ; add_sub_enh ; Untyped                                      ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                   ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                 ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                 ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                               ;
+------------------------+-------------+----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/vhdlpjt/clock/clock.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Wed Oct 29 17:46:43 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock
Info: Found 1 design units, including 1 entities, in source file clock.bdf
    Info: Found entity 1: clock
Info: Elaborating entity "clock" for the top level hierarchy
Warning: Pin "a" is missing source
Warning: Pin "b" is missing source
Warning: Pin "c" is missing source
Warning: Pin "d" is missing source
Warning: Pin "e" is missing source
Warning: Pin "f" is missing source
Warning: Pin "g" is missing source
Warning: Using design file alert.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: alert-fun
    Info: Found entity 1: alert
Info: Elaborating entity "alert" for hierarchy "alert:inst"
Warning (10492): VHDL Process Statement warning at alert.vhd(18): signal "count1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: Using design file minute.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: minute-fun
    Info: Found entity 1: minute
Info: Elaborating entity "minute" for hierarchy "minute:inst2"
Warning (10492): VHDL Process Statement warning at minute.vhd(19): signal "clk1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: Using design file second.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: second-fun
    Info: Found entity 1: second
Info: Elaborating entity "second" for hierarchy "second:inst3"
Warning: Using design file seltime.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: seltime-fun
    Info: Found entity 1: seltime
Info: Elaborating entity "seltime" for hierarchy "seltime:inst5"
Warning (10492): VHDL Process Statement warning at seltime.vhd(28): signal "count" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at seltime.vhd(29): signal "sec" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at seltime.vhd(31): signal "sec" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at seltime.vhd(32): signal "min" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at seltime.vhd(34): signal "min" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at seltime.vhd(35): signal "hour" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at seltime.vhd(37): signal "hour" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: Using design file hour.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: hour-fun
    Info: Found entity 1: hour
Info: Elaborating entity "hour" for hierarchy "hour:inst1"
Warning: Using design file deled.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: deled-fun
    Info: Found entity 1: deled
Info: Elaborating entity "deled" for hierarchy "deled:inst4"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "a" stuck at GND
    Warning: Pin "b" stuck at GND
    Warning: Pin "c" stuck at GND
    Warning: Pin "d" stuck at GND
    Warning: Pin "e" stuck at GND
    Warning: Pin "f" stuck at GND
    Warning: Pin "g" stuck at GND
Info: Implemented 88 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 14 output pins
    Info: Implemented 69 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 30 warnings
    Info: Processing ended: Wed Oct 29 17:46:49 2008
    Info: Elapsed time: 00:00:07