bu_ma.vhd

基于cyclone系列FPGA的模拟幅度调制的VHDL代码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
USE IEEE.STD_LOGIC_ARITH.ALL ;

ENTITY BU_MA IS 
PORT( DATA_IN : IN STD_LOGIC_VECTOR(9 DOWNTO 0 ) ;
      DATA_OUT : OUT STD_LOGIC_VECTOR(9 DOWNTO 0 )) ;
END ENTITY ;

ARCHITECTURE BUILDING OF BU_MA IS
SIGNAL TEMP_DATA_OUT : STD_LOGIC_VECTOR(9 DOWNTO 0 ) ; 
BEGIN
  DATA_OUT <= TEMP_DATA_OUT ;
  CODING : PROCESS(DATA_IN)
           BEGIN
             IF(DATA_IN(9) = '1') THEN
               TEMP_DATA_OUT <= '0' & DATA_IN(8 DOWNTO 0) ;
             ELSIF(DATA_IN(9) = '0') THEN
               TEMP_DATA_OUT <= '1' & DATA_IN(8 DOWNTO 0) ;
             END IF ;
           END PROCESS CODING ;
END ARCHITECTURE BUILDING ;