prev_cmp_fpga_am.qmsg

基于cyclone系列FPGA的模拟幅度调制的VHDL代码

{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_PLL_CLK_PROMOTION" "" "Info: Promoted PLL clock signals" { { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK" "LCK " "Info: Promoted signal \"LCK\" to use global clock" {  } { { "i:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "i:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCK" } { 0 "LCK" } } } } { "source/FPGA_AM_TEST.bdf" "" { Schematic "J:/FPGA/my_exercises/AM/project/source/FPGA_AM_TEST.bdf" { { 120 -520 -352 136 "LCK" "" } } } } { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCK } "NODE_NAME" } } { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCK } "NODE_NAME" } } { "i:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "i:/altera/72/quartus/bin/pin_planner.ppl" { LCK } } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK_USER" "altpll0_200M:inst6\|altpll:altpll_component\|_clk0 " "Info: Promoted signal \"altpll0_200M:inst6\|altpll:altpll_component\|_clk0\" to use global clock (user assigned)" {  } { { "i:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "i:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "altpll0_200M:inst6\|altpll:altpll_component\|_clk0" } } } } { "source/FPGA_AM_TEST.bdf" "" { Schematic "J:/FPGA/my_exercises/AM/project/source/FPGA_AM_TEST.bdf" { { 64 -312 -72 224 "inst6" "" } } } } { "altpll.tdf" "" { Text "i:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 585 3 0 } } { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0_200M:inst6|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0_200M:inst6|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock (user assigned)" 0 0 "" 0}  } {  } 0 0 "Promoted PLL clock signals" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "PLL Placement Operation " "Info: Completed PLL Placement Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLK_20M " "Warning: Node \"CLK_20M\" is assigned to location or region, but does not exist in design" {  } { { "i:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "i:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK_20M" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0}  } {  } 0 0 "Ignored locations or region assignments to the following nodes" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.412 ns register register " "Info: Estimated most critical path is register to register delay of 3.412 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CARRIER_507:inst16\|PHASE_WORD\[1\] 1 REG LAB_X11_Y4 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X11_Y4; Fanout = 14; REG Node = 'CARRIER_507:inst16\|PHASE_WORD\[1\]'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CARRIER_507:inst16|PHASE_WORD[1] } "NODE_NAME" } } { "source/CARRIER_KHZ507.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/CARRIER_KHZ507.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.699 ns) + CELL(0.575 ns) 1.274 ns CARRIER_507:inst16\|Add0~135COUT1 2 COMB LAB_X10_Y4 2 " "Info: 2: + IC(0.699 ns) + CELL(0.575 ns) = 1.274 ns; Loc. = LAB_X10_Y4; Fanout = 2; COMB Node = 'CARRIER_507:inst16\|Add0~135COUT1'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.274 ns" { CARRIER_507:inst16|PHASE_WORD[1] CARRIER_507:inst16|Add0~135COUT1 } "NODE_NAME" } } { "i:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "i:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.354 ns CARRIER_507:inst16\|Add0~137COUT1 3 COMB LAB_X10_Y4 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.354 ns; Loc. = LAB_X10_Y4; Fanout = 2; COMB Node = 'CARRIER_507:inst16\|Add0~137COUT1'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { CARRIER_507:inst16|Add0~135COUT1 CARRIER_507:inst16|Add0~137COUT1 } "NODE_NAME" } } { "i:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "i:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.434 ns CARRIER_507:inst16\|Add0~139COUT1 4 COMB LAB_X10_Y4 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.434 ns; Loc. = LAB_X10_Y4; Fanout = 2; COMB Node = 'CARRIER_507:inst16\|Add0~139COUT1'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { CARRIER_507:inst16|Add0~137COUT1 CARRIER_507:inst16|Add0~139COUT1 } "NODE_NAME" } } { "i:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "i:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.692 ns CARRIER_507:inst16\|Add0~141 5 COMB LAB_X10_Y4 4 " "Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 1.692 ns; Loc. = LAB_X10_Y4; Fanout = 4; COMB Node = 'CARRIER_507:inst16\|Add0~141'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.258 ns" { CARRIER_507:inst16|Add0~139COUT1 CARRIER_507:inst16|Add0~141 } "NODE_NAME" } } { "i:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "i:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.679 ns) 2.371 ns CARRIER_507:inst16\|Add0~142 6 COMB LAB_X10_Y4 1 " "Info: 6: + IC(0.000 ns) + CELL(0.679 ns) = 2.371 ns; Loc. = LAB_X10_Y4; Fanout = 1; COMB Node = 'CARRIER_507:inst16\|Add0~142'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.679 ns" { CARRIER_507:inst16|Add0~141 CARRIER_507:inst16|Add0~142 } "NODE_NAME" } } { "i:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "i:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.303 ns) + CELL(0.738 ns) 3.412 ns CARRIER_507:inst16\|PHASE_WORD\[5\] 7 REG LAB_X11_Y4 14 " "Info: 7: + IC(0.303 ns) + CELL(0.738 ns) = 3.412 ns; Loc. = LAB_X11_Y4; Fanout = 14; REG Node = 'CARRIER_507:inst16\|PHASE_WORD\[5\]'" {  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.041 ns" { CARRIER_507:inst16|Add0~142 CARRIER_507:inst16|PHASE_WORD[5] } "NODE_NAME" } } { "source/CARRIER_KHZ507.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/source/CARRIER_KHZ507.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.410 ns ( 70.63 % ) " "Info: Total cell delay = 2.410 ns ( 70.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.002 ns ( 29.37 % ) " "Info: Total interconnect delay = 1.002 ns ( 29.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "i:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.412 ns" { CARRIER_507:inst16|PHASE_WORD[1] CARRIER_507:inst16|Add0~135COUT1 CARRIER_507:inst16|Add0~137COUT1 CARRIER_507:inst16|Add0~139COUT1 CARRIER_507:inst16|Add0~141 CARRIER_507:inst16|Add0~142 CARRIER_507:inst16|PHASE_WORD[5] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "2 " "Info: Average interconnect usage is 2% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "4 X0_Y0 X13_Y14 " "Info: Peak interconnect usage is 4% of the available device resources in the region that extends from location X0_Y0 to location X13_Y14" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitt