prev_cmp_fpga_am.map.qmsg

基于cyclone系列FPGA的模拟幅度调制的VHDL代码

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CARRIER_507 CARRIER_507:inst16 " "Info: Elaborating entity \"CARRIER_507\" for hierarchy \"CARRIER_507:inst16\"" {  } { { "source/FPGA_AM_TEST.bdf" "inst16" { Schematic "J:/FPGA/my_exercises/AM/project/source/FPGA_AM_TEST.bdf" { { 96 8 168 192 "inst16" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "ADD256.vhd 2 1 " "Warning: Using design file ADD256.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 add256-SYN " "Info: Found design unit 1: add256-SYN" {  } { { "ADD256.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/ADD256.vhd" 52 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 ADD256 " "Info: Found entity 1: ADD256" {  } { { "ADD256.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/ADD256.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ADD256 ADD256:inst12 " "Info: Elaborating entity \"ADD256\" for hierarchy \"ADD256:inst12\"" {  } { { "source/FPGA_AM_TEST.bdf" "inst12" { Schematic "J:/FPGA/my_exercises/AM/project/source/FPGA_AM_TEST.bdf" { { 352 272 432 448 "inst12" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub ADD256:inst12\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"ADD256:inst12\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "ADD256.vhd" "lpm_add_sub_component" { Text "J:/FPGA/my_exercises/AM/project/ADD256.vhd" 75 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "ADD256:inst12\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborated megafunction instantiation \"ADD256:inst12\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "ADD256.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/ADD256.vhd" 75 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "lAM_FUDU.vhd 2 1 " "Warning: Using design file lAM_FUDU.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lam_fudu-SYN " "Info: Found design unit 1: lam_fudu-SYN" {  } { { "lAM_FUDU.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/lAM_FUDU.vhd" 52 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 lAM_FUDU " "Info: Found entity 1: lAM_FUDU" {  } { { "lAM_FUDU.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/lAM_FUDU.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lAM_FUDU lAM_FUDU:inst10 " "Info: Elaborating entity \"lAM_FUDU\" for hierarchy \"lAM_FUDU:inst10\"" {  } { { "source/FPGA_AM_TEST.bdf" "inst10" { Schematic "J:/FPGA/my_exercises/AM/project/source/FPGA_AM_TEST.bdf" { { 352 48 216 448 "inst10" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "CON_256.vhd 2 1 " "Warning: Using design file CON_256.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 con_256-SYN " "Info: Found design unit 1: con_256-SYN" {  } { { "CON_256.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/CON_256.vhd" 50 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 CON_256 " "Info: Found entity 1: CON_256" {  } { { "CON_256.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/CON_256.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CON_256 CON_256:inst11 " "Info: Elaborating entity \"CON_256\" for hierarchy \"CON_256:inst11\"" {  } { { "source/FPGA_AM_TEST.bdf" "inst11" { Schematic "J:/FPGA/my_exercises/AM/project/source/FPGA_AM_TEST.bdf" { { 368 -32 32 416 "inst11" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i:/altera/72/quartus/libraries/megafunctions/lpm_constant.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file i:/altera/72/quartus/libraries/megafunctions/lpm_constant.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_constant " "Info: Found entity 1: lpm_constant" {  } { { "lpm_constant.tdf" "" { Text "i:/altera/72/quartus/libraries/megafunctions/lpm_constant.tdf" 39 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_constant CON_256:inst11\|lpm_constant:lpm_constant_component " "Info: Elaborating entity \"lpm_constant\" for hierarchy \"CON_256:inst11\|lpm_constant:lpm_constant_component\"" {  } { { "CON_256.vhd" "lpm_constant_component" { Text "J:/FPGA/my_exercises/AM/project/CON_256.vhd" 71 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "CON_256:inst11\|lpm_constant:lpm_constant_component " "Info: Elaborated megafunction instantiation \"CON_256:inst11\|lpm_constant:lpm_constant_component\"" {  } { { "CON_256.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/CON_256.vhd" 71 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "CARRIER_ROM.vhd 2 1 " "Warning: Using design file CARRIER_ROM.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 carrier_rom-SYN " "Info: Found design unit 1: carrier_rom-SYN" {  } { { "CARRIER_ROM.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/CARRIER_ROM.vhd" 52 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 CARRIER_ROM " "Info: Found entity 1: CARRIER_ROM" {  } { { "CARRIER_ROM.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/CARRIER_ROM.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CARRIER_ROM CARRIER_ROM:inst3 " "Info: Elaborating entity \"CARRIER_ROM\" for hierarchy \"CARRIER_ROM:inst3\"" {  } { { "source/FPGA_AM_TEST.bdf" "inst3" { Schematic "J:/FPGA/my_exercises/AM/project/source/FPGA_AM_TEST.bdf" { { 512 112 328 648 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram CARRIER_ROM:inst3\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"CARRIER_ROM:inst3\|altsyncram:altsyncram_component\"" {  } { { "CARRIER_ROM.vhd" "altsyncram_component" { Text "J:/FPGA/my_exercises/AM/project/CARRIER_ROM.vhd" 84 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "CARRIER_ROM:inst3\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"CARRIER_ROM:inst3\|altsyncram:altsyncram_component\"" {  } { { "CARRIER_ROM.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/CARRIER_ROM.vhd" 84 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_u981.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_u981.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_u981 " "Info: Found entity 1: altsyncram_u981" {  } { { "db/altsyncram_u981.tdf" "" { Text "J:/FPGA/my_exercises/AM/project/db/altsyncram_u981.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_u981 CARRIER_ROM:inst3\|altsyncram:altsyncram_component\|altsyncram_u981:auto_generated " "Info: Elaborating entity \"altsyncram_u981\" for hierarchy \"CARRIER_ROM:inst3\|altsyncram:altsyncram_component\|altsyncram_u981:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "i:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MODEM MODEM:inst4 " "Info: Elaborating entity \"MODEM\" for hierarchy \"MODEM:inst4\"" {  } { { "source/FPGA_AM_TEST.bdf" "inst4" { Schematic "J:/FPGA/my_exercises/AM/project/source/FPGA_AM_TEST.bdf" { { 512 -96 104 608 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "lAD256.vhd 2 1 " "Warning: Using design file lAD256.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lad256-SYN " "Info: Found design unit 1: lad256-SYN" {  } { { "lAD256.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/lAD256.vhd" 50 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 lAD256 " "Info: Found entity 1: lAD256" {  } { { "lAD256.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/lAD256.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lAD256 lAD256:inst13 " "Info: Elaborating entity \"lAD256\" for hierarchy \"lAD256:inst13\"" {  } { { "source/FPGA_AM_TEST.bdf" "inst13" { Schematic "J:/FPGA/my_exercises/AM/project/source/FPGA_AM_TEST.bdf" { { 432 192 256 480 "inst13" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_constant lAD256:inst13\|lpm_constant:lpm_constant_component " "Info: Elaborating entity \"lpm_constant\" for hierarchy \"lAD256:inst13\|lpm_constant:lpm_constant_component\"" {  } { { "lAD256.vhd" "lpm_constant_component" { Text "J:/FPGA/my_exercises/AM/project/lAD256.vhd" 71 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lAD256:inst13\|lpm_constant:lpm_constant_component " "Info: Elaborated megafunction instantiation \"lAD256:inst13\|lpm_constant:lpm_constant_component\"" {  } { { "lAD256.vhd" "" { Text "J:/FPGA/my_exercises/AM/project/lAD256.vhd" 71 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "316 " "Info: Ignored 316 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "316 " "Info: Ignored 316 SOFT buffer(s)" {  } {  } 0 0 "Ignored %1!d! SOFT buffer(s)" 0 0 "" 0}  } {  } 0 0 "Ignored %1!d! buffer(s)" 0 0 "" 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "234 " "Info: Ignored 234 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "234 " "Info: Ignored 234 SOFT buffer(s)" {  } {  } 0 0 "Ignored %1!d! SOFT buffer(s)" 0 0 "" 0}  } {  } 0 0 "Ignored %1!d! buffer(s)" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "312 " "Info: Implemented 312 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "11 " "Info: Implemented 11 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "278 " "Info: Implemented 278 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0} { "Info" "ICUT_CUT_TM_RAMS" "20 " "Info: Implemented 20 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Info: Implemented 1 ClockLock PLLs" {  } {  } 0 0 "Implemented %1!d! ClockLock PLLs" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "171 " "Info: Allocated 171 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 27 15:42:43 2008 " "Info: Processing ended: Wed Aug 27 15:42:43 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}