📄 lpm_rom0_394_altsyncram.v
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.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_4.connectivity_checking = "OFF",
ram_block1a_4.init_file = "./source/FPGA_AM_394.mif",
ram_block1a_4.init_file_layout = "port_a",
ram_block1a_4.logical_ram_name = "ALTSYNCRAM",
ram_block1a_4.mem_init0 = 394'h26666633398C71C70F83F00000000FC1F0E38E319CCC6666664CCCE666338C71C3C3E03FFFFFFF01F0F0E38C731999CCCC9,
ram_block1a_4.operation_mode = "rom",
ram_block1a_4.port_a_address_clear = "none",
ram_block1a_4.port_a_address_width = 9,
ram_block1a_4.port_a_data_out_clear = "none",
ram_block1a_4.port_a_data_out_clock = "none",
ram_block1a_4.port_a_data_width = 1,
ram_block1a_4.port_a_first_address = 0,
ram_block1a_4.port_a_first_bit_number = 4,
ram_block1a_4.port_a_last_address = 393,
ram_block1a_4.port_a_logical_ram_depth = 394,
ram_block1a_4.port_a_logical_ram_width = 10,
ram_block1a_4.ram_block_type = "M4K",
ram_block1a_4.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block1a_5
(
.clk0(clock0),
.portaaddr({address_a_wire[8:0]}),
.portadataout(wire_ram_block1a_5portadataout[0:0]),
.portbdataout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portabyteenamasks({1{1'b1}}),
.portadatain({1{1'b0}}),
.portawe(1'b0),
.portbaddr({1{1'b0}}),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbrewe(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_5.connectivity_checking = "OFF",
ram_block1a_5.init_file = "./source/FPGA_AM_394.mif",
ram_block1a_5.init_file_layout = "port_a",
ram_block1a_5.logical_ram_name = "ALTSYNCRAM",
ram_block1a_5.mem_init0 = 394'h3878783C3E0F81F80FFC00000000003FF01F81F07C3C1E1E1E3C3C1E1E0F83F03FC01FFFFFFFFFFE00FF03F07C1E1E0F0F1,
ram_block1a_5.operation_mode = "rom",
ram_block1a_5.port_a_address_clear = "none",
ram_block1a_5.port_a_address_width = 9,
ram_block1a_5.port_a_data_out_clear = "none",
ram_block1a_5.port_a_data_out_clock = "none",
ram_block1a_5.port_a_data_width = 1,
ram_block1a_5.port_a_first_address = 0,
ram_block1a_5.port_a_first_bit_number = 5,
ram_block1a_5.port_a_last_address = 393,
ram_block1a_5.port_a_logical_ram_depth = 394,
ram_block1a_5.port_a_logical_ram_width = 10,
ram_block1a_5.ram_block_type = "M4K",
ram_block1a_5.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block1a_6
(
.clk0(clock0),
.portaaddr({address_a_wire[8:0]}),
.portadataout(wire_ram_block1a_6portadataout[0:0]),
.portbdataout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portabyteenamasks({1{1'b1}}),
.portadatain({1{1'b0}}),
.portawe(1'b0),
.portbaddr({1{1'b0}}),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbrewe(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_6.connectivity_checking = "OFF",
ram_block1a_6.init_file = "./source/FPGA_AM_394.mif",
ram_block1a_6.init_file_layout = "port_a",
ram_block1a_6.logical_ram_name = "ALTSYNCRAM",
ram_block1a_6.mem_init0 = 394'h3F807FC03FF001FFF0000000000000000FFF800FFC03FE01FE03FC01FE007FF0003FFFFFFFFFFFFFFF0003FF801FE00FF01,
ram_block1a_6.operation_mode = "rom",
ram_block1a_6.port_a_address_clear = "none",
ram_block1a_6.port_a_address_width = 9,
ram_block1a_6.port_a_data_out_clear = "none",
ram_block1a_6.port_a_data_out_clock = "none",
ram_block1a_6.port_a_data_width = 1,
ram_block1a_6.port_a_first_address = 0,
ram_block1a_6.port_a_first_bit_number = 6,
ram_block1a_6.port_a_last_address = 393,
ram_block1a_6.port_a_logical_ram_depth = 394,
ram_block1a_6.port_a_logical_ram_width = 10,
ram_block1a_6.ram_block_type = "M4K",
ram_block1a_6.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block1a_7
(
.clk0(clock0),
.portaaddr({address_a_wire[8:0]}),
.portadataout(wire_ram_block1a_7portadataout[0:0]),
.portbdataout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portabyteenamasks({1{1'b1}}),
.portadatain({1{1'b0}}),
.portawe(1'b0),
.portbaddr({1{1'b0}}),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbrewe(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_7.connectivity_checking = "OFF",
ram_block1a_7.init_file = "./source/FPGA_AM_394.mif",
ram_block1a_7.init_file_layout = "port_a",
ram_block1a_7.logical_ram_name = "ALTSYNCRAM",
ram_block1a_7.mem_init0 = 394'h3FFF80003FFFFE00000000000000000000007FFFFC0001FFFE0003FFFE00000FFFFFFFFFFFFFFFFFFFFFFC00001FFFF0001,
ram_block1a_7.operation_mode = "rom",
ram_block1a_7.port_a_address_clear = "none",
ram_block1a_7.port_a_address_width = 9,
ram_block1a_7.port_a_data_out_clear = "none",
ram_block1a_7.port_a_data_out_clock = "none",
ram_block1a_7.port_a_data_width = 1,
ram_block1a_7.port_a_first_address = 0,
ram_block1a_7.port_a_first_bit_number = 7,
ram_block1a_7.port_a_last_address = 393,
ram_block1a_7.port_a_logical_ram_depth = 394,
ram_block1a_7.port_a_logical_ram_width = 10,
ram_block1a_7.ram_block_type = "M4K",
ram_block1a_7.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block1a_8
(
.clk0(clock0),
.portaaddr({address_a_wire[8:0]}),
.portadataout(wire_ram_block1a_8portadataout[0:0]),
.portbdataout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portabyteenamasks({1{1'b1}}),
.portadatain({1{1'b0}}),
.portawe(1'b0),
.portbaddr({1{1'b0}}),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbrewe(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_8.connectivity_checking = "OFF",
ram_block1a_8.init_file = "./source/FPGA_AM_394.mif",
ram_block1a_8.init_file_layout = "port_a",
ram_block1a_8.logical_ram_name = "ALTSYNCRAM",
ram_block1a_8.mem_init0 = 394'h3FFFFFFFC000000000000000000000000000000003FFFFFFFE00000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000001,
ram_block1a_8.operation_mode = "rom",
ram_block1a_8.port_a_address_clear = "none",
ram_block1a_8.port_a_address_width = 9,
ram_block1a_8.port_a_data_out_clear = "none",
ram_block1a_8.port_a_data_out_clock = "none",
ram_block1a_8.port_a_data_width = 1,
ram_block1a_8.port_a_first_address = 0,
ram_block1a_8.port_a_first_bit_number = 8,
ram_block1a_8.port_a_last_address = 393,
ram_block1a_8.port_a_logical_ram_depth = 394,
ram_block1a_8.port_a_logical_ram_width = 10,
ram_block1a_8.ram_block_type = "M4K",
ram_block1a_8.lpm_type = "cyclone_ram_block";
cyclone_ram_block ram_block1a_9
(
.clk0(clock0),
.portaaddr({address_a_wire[8:0]}),
.portadataout(wire_ram_block1a_9portadataout[0:0]),
.portbdataout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portabyteenamasks({1{1'b1}}),
.portadatain({1{1'b0}}),
.portawe(1'b0),
.portbaddr({1{1'b0}}),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbrewe(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_9.connectivity_checking = "OFF",
ram_block1a_9.init_file = "./source/FPGA_AM_394.mif",
ram_block1a_9.init_file_layout = "port_a",
ram_block1a_9.logical_ram_name = "ALTSYNCRAM",
ram_block1a_9.mem_init0 = 394'h00000000000000000000000000000000000000000000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE,
ram_block1a_9.operation_mode = "rom",
ram_block1a_9.port_a_address_clear = "none",
ram_block1a_9.port_a_address_width = 9,
ram_block1a_9.port_a_data_out_clear = "none",
ram_block1a_9.port_a_data_out_clock = "none",
ram_block1a_9.port_a_data_width = 1,
ram_block1a_9.port_a_first_address = 0,
ram_block1a_9.port_a_first_bit_number = 9,
ram_block1a_9.port_a_last_address = 393,
ram_block1a_9.port_a_logical_ram_depth = 394,
ram_block1a_9.port_a_logical_ram_width = 10,
ram_block1a_9.ram_block_type = "M4K",
ram_block1a_9.lpm_type = "cyclone_ram_block";
assign
address_a_wire = address_a,
q_a = {wire_ram_block1a_9portadataout[0], wire_ram_block1a_8portadataout[0], wire_ram_block1a_7portadataout[0], wire_ram_block1a_6portadataout[0], wire_ram_block1a_5portadataout[0], wire_ram_block1a_4portadataout[0], wire_ram_block1a_3portadataout[0], wire_ram_block1a_2portadataout[0], wire_ram_block1a_1portadataout[0], wire_ram_block1a_0portadataout[0]};
endmodule //lpm_rom0_394_altsyncram
//VALID FILE
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