lpm_rom0_394_altsyncram.v

基于cyclone系列FPGA的模拟幅度调制的VHDL代码

//altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone" ENABLE_RUNTIME_MOD="NO" INIT_FILE="./source/FPGA_AM_394.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=394 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="UNREGISTERED" RAM_BLOCK_TYPE="M4K" WIDTH_A=10 WIDTH_BYTEENA_A=1 WIDTHAD_A=9 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
//VERSION_BEGIN 7.2 cbx_altsyncram 2007:08:27:07:35:30:SJ cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_compare 2007:06:21:15:54:06:SJ cbx_lpm_decode 2007:03:12:19:01:52:SJ cbx_lpm_mux 2007:05:11:14:07:38:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:05:02:16:27:14:SJ cbx_stratixii 2007:06:28:17:26:26:SJ cbx_stratixiii 2007:06:28:17:15:56:SJ cbx_util_mgl 2007:06:01:06:37:30:SJ  VERSION_END
//CBXI_INSTANCE_NAME="FPGA_AM_TEST_lpm_rom0_394_inst9_altsyncram_altsyncram_component"
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



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//synthesis_resources = M4K 2 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  lpm_rom0_394_altsyncram
	( 
	address_a,
	clock0,
	q_a) /* synthesis synthesis_clearbox=1 */
		/* synthesis ALTERA_ATTRIBUTE="OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION" */;
	input   [8:0]  address_a;
	input   clock0;
	output   [9:0]  q_a;

	wire  [0:0]   wire_ram_block1a_0portadataout;
	wire  [0:0]   wire_ram_block1a_1portadataout;
	wire  [0:0]   wire_ram_block1a_2portadataout;
	wire  [0:0]   wire_ram_block1a_3portadataout;
	wire  [0:0]   wire_ram_block1a_4portadataout;
	wire  [0:0]   wire_ram_block1a_5portadataout;
	wire  [0:0]   wire_ram_block1a_6portadataout;
	wire  [0:0]   wire_ram_block1a_7portadataout;
	wire  [0:0]   wire_ram_block1a_8portadataout;
	wire  [0:0]   wire_ram_block1a_9portadataout;
	wire  [8:0]  address_a_wire;

	cyclone_ram_block   ram_block1a_0
	( 
	.clk0(clock0),
	.portaaddr({address_a_wire[8:0]}),
	.portadataout(wire_ram_block1a_0portadataout[0:0]),
	.portbdataout()
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.clk1(1'b0),
	.clr0(1'b0),
	.clr1(1'b0),
	.ena0(1'b1),
	.ena1(1'b1),
	.portabyteenamasks({1{1'b1}}),
	.portadatain({1{1'b0}}),
	.portawe(1'b0),
	.portbaddr({1{1'b0}}),
	.portbbyteenamasks({1{1'b1}}),
	.portbdatain({1{1'b0}}),
	.portbrewe(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(1'b1),
	.devpor(1'b1)
	// synopsys translate_on
	);
	defparam
		ram_block1a_0.connectivity_checking = "OFF",
		ram_block1a_0.init_file = "./source/FPGA_AM_394.mif",
		ram_block1a_0.init_file_layout = "port_a",
		ram_block1a_0.logical_ram_name = "ALTSYNCRAM",
		ram_block1a_0.mem_init0 = 394'h38000712549FF974FF6B3E6B00D67CD4FF2E9FF92A48E0001FC0003892A4FFCBA7F959F35806B3E6A7F974FFC952470000F,
		ram_block1a_0.operation_mode = "rom",
		ram_block1a_0.port_a_address_clear = "none",
		ram_block1a_0.port_a_address_width = 9,
		ram_block1a_0.port_a_data_out_clear = "none",
		ram_block1a_0.port_a_data_out_clock = "none",
		ram_block1a_0.port_a_data_width = 1,
		ram_block1a_0.port_a_first_address = 0,
		ram_block1a_0.port_a_first_bit_number = 0,
		ram_block1a_0.port_a_last_address = 393,
		ram_block1a_0.port_a_logical_ram_depth = 394,
		ram_block1a_0.port_a_logical_ram_width = 10,
		ram_block1a_0.ram_block_type = "M4K",
		ram_block1a_0.lpm_type = "cyclone_ram_block";
	cyclone_ram_block   ram_block1a_1
	( 
	.clk0(clock0),
	.portaaddr({address_a_wire[8:0]}),
	.portadataout(wire_ram_block1a_1portadataout[0:0]),
	.portbdataout()
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.clk1(1'b0),
	.clr0(1'b0),
	.clr1(1'b0),
	.ena0(1'b1),
	.ena1(1'b1),
	.portabyteenamasks({1{1'b1}}),
	.portadatain({1{1'b0}}),
	.portawe(1'b0),
	.portbaddr({1{1'b0}}),
	.portbbyteenamasks({1{1'b1}}),
	.portbdatain({1{1'b0}}),
	.portbrewe(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(1'b1),
	.devpor(1'b1)
	// synopsys translate_on
	);
	defparam
		ram_block1a_1.connectivity_checking = "OFF",
		ram_block1a_1.init_file = "./source/FPGA_AM_394.mif",
		ram_block1a_1.init_file_layout = "port_a",
		ram_block1a_1.logical_ram_name = "ALTSYNCRAM",
		ram_block1a_1.mem_init0 = 394'h3FFFFF0E324AADB8FF196B4C0032D698FF1DB5524C70FFFFFFC0003F1CC955599FFE6D56C7F8DAAD9FFE66AAA4CE3F0000F,
		ram_block1a_1.operation_mode = "rom",
		ram_block1a_1.port_a_address_clear = "none",
		ram_block1a_1.port_a_address_width = 9,
		ram_block1a_1.port_a_data_out_clear = "none",
		ram_block1a_1.port_a_data_out_clock = "none",
		ram_block1a_1.port_a_data_width = 1,
		ram_block1a_1.port_a_first_address = 0,
		ram_block1a_1.port_a_first_bit_number = 1,
		ram_block1a_1.port_a_last_address = 393,
		ram_block1a_1.port_a_logical_ram_depth = 394,
		ram_block1a_1.port_a_logical_ram_width = 10,
		ram_block1a_1.ram_block_type = "M4K",
		ram_block1a_1.lpm_type = "cyclone_ram_block";
	cyclone_ram_block   ram_block1a_2
	( 
	.clk0(clock0),
	.portaaddr({address_a_wire[8:0]}),
	.portadataout(wire_ram_block1a_2portadataout[0:0]),
	.portbdataout()
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.clk1(1'b0),
	.clr0(1'b0),
	.clr1(1'b0),
	.ena0(1'b1),
	.ena1(1'b1),
	.portabyteenamasks({1{1'b1}}),
	.portadatain({1{1'b0}}),
	.portawe(1'b0),
	.portbaddr({1{1'b0}}),
	.portbbyteenamasks({1{1'b1}}),
	.portbdatain({1{1'b0}}),
	.portbrewe(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(1'b1),
	.devpor(1'b1)
	// synopsys translate_on
	);
	defparam
		ram_block1a_2.connectivity_checking = "OFF",
		ram_block1a_2.init_file = "./source/FPGA_AM_394.mif",
		ram_block1a_2.init_file_layout = "port_a",
		ram_block1a_2.logical_ram_name = "ALTSYNCRAM",
		ram_block1a_2.mem_init0 = 394'h3FFFFF01F1C66495AA524C70000E324A55A926638F80FFFFFFC0003FE0F19992D55524CE3FFF1CC92AAAD26663C1FF0000F,
		ram_block1a_2.operation_mode = "rom",
		ram_block1a_2.port_a_address_clear = "none",
		ram_block1a_2.port_a_address_width = 9,
		ram_block1a_2.port_a_data_out_clear = "none",
		ram_block1a_2.port_a_data_out_clock = "none",
		ram_block1a_2.port_a_data_width = 1,
		ram_block1a_2.port_a_first_address = 0,
		ram_block1a_2.port_a_first_bit_number = 2,
		ram_block1a_2.port_a_last_address = 393,
		ram_block1a_2.port_a_logical_ram_depth = 394,
		ram_block1a_2.port_a_logical_ram_width = 10,
		ram_block1a_2.ram_block_type = "M4K",
		ram_block1a_2.lpm_type = "cyclone_ram_block";
	cyclone_ram_block   ram_block1a_3
	( 
	.clk0(clock0),
	.portaaddr({address_a_wire[8:0]}),
	.portadataout(wire_ram_block1a_3portadataout[0:0]),
	.portbdataout()
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.clk1(1'b0),
	.clr0(1'b0),
	.clr1(1'b0),
	.ena0(1'b1),
	.ena1(1'b1),
	.portabyteenamasks({1{1'b1}}),
	.portadatain({1{1'b0}}),
	.portawe(1'b0),
	.portbaddr({1{1'b0}}),
	.portbbyteenamasks({1{1'b1}}),
	.portbdatain({1{1'b0}}),
	.portbrewe(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(1'b1),
	.devpor(1'b1)
	// synopsys translate_on
	);
	defparam
		ram_block1a_3.connectivity_checking = "OFF",
		ram_block1a_3.init_file = "./source/FPGA_AM_394.mif",
		ram_block1a_3.init_file_layout = "port_a",
		ram_block1a_3.logical_ram_name = "ALTSYNCRAM",
		ram_block1a_3.mem_init0 = 394'h155555AAA56B4926CC638F800001F1C6336492D6A555AAAAAA95556AAA54B4B64CCCE3C1FFFFE0F1CCCC9B4B4A9555AAAA5,
		ram_block1a_3.operation_mode = "rom",
		ram_block1a_3.port_a_address_clear = "none",
		ram_block1a_3.port_a_address_width = 9,
		ram_block1a_3.port_a_data_out_clear = "none",
		ram_block1a_3.port_a_data_out_clock = "none",
		ram_block1a_3.port_a_data_width = 1,
		ram_block1a_3.port_a_first_address = 0,
		ram_block1a_3.port_a_first_bit_number = 3,
		ram_block1a_3.port_a_last_address = 393,
		ram_block1a_3.port_a_logical_ram_depth = 394,
		ram_block1a_3.port_a_logical_ram_width = 10,
		ram_block1a_3.ram_block_type = "M4K",
		ram_block1a_3.lpm_type = "cyclone_ram_block";
	cyclone_ram_block   ram_block1a_4
	( 
	.clk0(clock0),
	.portaaddr({address_a_wire[8:0]}),
	.portadataout(wire_ram_block1a_4portadataout[0:0]),
	.portbdataout()
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.clk1(1'b0),
	.clr0(1'b0),
	.clr1(1'b0),
	.ena0(1'b1),
	.ena1(1'b1),
	.portabyteenamasks({1{1'b1}}),
	.portadatain({1{1'b0}}),
	.portawe(1'b0),
	.portbaddr({1{1'b0}}),
	.portbbyteenamasks({1{1'b1}}),
	.portbdatain({1{1'b0}}),
	.portbrewe(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(1'b1),