fpga_am.sim.rpt

基于cyclone系列FPGA的模拟幅度调制的VHDL代码

; |FPGA_AM_TEST|CARRIER:inst2|PHASE_WORD[9]                                                                   ; |FPGA_AM_TEST|CARRIER:inst2|PHASE_WORD[9]                                                             ; regout           ;
; |FPGA_AM_TEST|CARRIER_ROM:inst1|altsyncram:altsyncram_component|altsyncram_u981:auto_generated|ram_block1a0 ; |FPGA_AM_TEST|CARRIER_ROM:inst1|altsyncram:altsyncram_component|altsyncram_u981:auto_generated|q_a[0] ; portadataout0    ;
; |FPGA_AM_TEST|CARRIER_ROM:inst1|altsyncram:altsyncram_component|altsyncram_u981:auto_generated|ram_block1a1 ; |FPGA_AM_TEST|CARRIER_ROM:inst1|altsyncram:altsyncram_component|altsyncram_u981:auto_generated|q_a[1] ; portadataout0    ;
; |FPGA_AM_TEST|CARRIER_ROM:inst1|altsyncram:altsyncram_component|altsyncram_u981:auto_generated|ram_block1a2 ; |FPGA_AM_TEST|CARRIER_ROM:inst1|altsyncram:altsyncram_component|altsyncram_u981:auto_generated|q_a[2] ; portadataout0    ;
; |FPGA_AM_TEST|CARRIER_ROM:inst1|altsyncram:altsyncram_component|altsyncram_u981:auto_generated|ram_block1a3 ; |FPGA_AM_TEST|CARRIER_ROM:inst1|altsyncram:altsyncram_component|altsyncram_u981:auto_generated|q_a[3] ; portadataout0    ;
; |FPGA_AM_TEST|CARRIER_ROM:inst1|altsyncram:altsyncram_component|altsyncram_u981:auto_generated|ram_block1a4 ; |FPGA_AM_TEST|CARRIER_ROM:inst1|altsyncram:altsyncram_component|altsyncram_u981:auto_generated|q_a[4] ; portadataout0    ;
; |FPGA_AM_TEST|CARRIER_ROM:inst1|altsyncram:altsyncram_component|altsyncram_u981:auto_generated|ram_block1a5 ; |FPGA_AM_TEST|CARRIER_ROM:inst1|altsyncram:altsyncram_component|altsyncram_u981:auto_generated|q_a[5] ; portadataout0    ;
; |FPGA_AM_TEST|CARRIER_ROM:inst1|altsyncram:altsyncram_component|altsyncram_u981:auto_generated|ram_block1a6 ; |FPGA_AM_TEST|CARRIER_ROM:inst1|altsyncram:altsyncram_component|altsyncram_u981:auto_generated|q_a[6] ; portadataout0    ;
; |FPGA_AM_TEST|CARRIER_ROM:inst1|altsyncram:altsyncram_component|altsyncram_u981:auto_generated|ram_block1a7 ; |FPGA_AM_TEST|CARRIER_ROM:inst1|altsyncram:altsyncram_component|altsyncram_u981:auto_generated|q_a[7] ; portadataout0    ;
; |FPGA_AM_TEST|CARRIER_ROM:inst1|altsyncram:altsyncram_component|altsyncram_u981:auto_generated|ram_block1a8 ; |FPGA_AM_TEST|CARRIER_ROM:inst1|altsyncram:altsyncram_component|altsyncram_u981:auto_generated|q_a[8] ; portadataout0    ;
; |FPGA_AM_TEST|CARRIER_ROM:inst1|altsyncram:altsyncram_component|altsyncram_u981:auto_generated|ram_block1a9 ; |FPGA_AM_TEST|CARRIER_ROM:inst1|altsyncram:altsyncram_component|altsyncram_u981:auto_generated|q_a[9] ; portadataout0    ;
; |FPGA_AM_TEST|BU_MA:inst|DATA_OUT[9]                                                                        ; |FPGA_AM_TEST|BU_MA:inst|DATA_OUT[9]                                                                  ; out              ;
; |FPGA_AM_TEST|BU_MA:inst|DATA_OUT[8]                                                                        ; |FPGA_AM_TEST|BU_MA:inst|DATA_OUT[8]                                                                  ; out              ;
; |FPGA_AM_TEST|BU_MA:inst|DATA_OUT[7]                                                                        ; |FPGA_AM_TEST|BU_MA:inst|DATA_OUT[7]                                                                  ; out              ;
; |FPGA_AM_TEST|BU_MA:inst|DATA_OUT[6]                                                                        ; |FPGA_AM_TEST|BU_MA:inst|DATA_OUT[6]                                                                  ; out              ;
; |FPGA_AM_TEST|BU_MA:inst|DATA_OUT[5]                                                                        ; |FPGA_AM_TEST|BU_MA:inst|DATA_OUT[5]                                                                  ; out              ;
; |FPGA_AM_TEST|BU_MA:inst|DATA_OUT[4]                                                                        ; |FPGA_AM_TEST|BU_MA:inst|DATA_OUT[4]                                                                  ; out              ;
; |FPGA_AM_TEST|BU_MA:inst|DATA_OUT[3]                                                                        ; |FPGA_AM_TEST|BU_MA:inst|DATA_OUT[3]                                                                  ; out              ;
; |FPGA_AM_TEST|BU_MA:inst|DATA_OUT[2]                                                                        ; |FPGA_AM_TEST|BU_MA:inst|DATA_OUT[2]                                                                  ; out              ;
; |FPGA_AM_TEST|BU_MA:inst|DATA_OUT[1]                                                                        ; |FPGA_AM_TEST|BU_MA:inst|DATA_OUT[1]                                                                  ; out              ;
; |FPGA_AM_TEST|BU_MA:inst|DATA_OUT[0]                                                                        ; |FPGA_AM_TEST|BU_MA:inst|DATA_OUT[0]                                                                  ; out              ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|result_node[0]                                                    ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|result_node[0]                                              ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|result_node[1]                                                    ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|result_node[1]                                              ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|result_node[2]                                                    ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|result_node[2]                                              ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|result_node[3]                                                    ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|result_node[3]                                              ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|result_node[4]                                                    ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|result_node[4]                                              ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|result_node[5]                                                    ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|result_node[5]                                              ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|result_node[6]                                                    ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|result_node[6]                                              ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|result_node[7]                                                    ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|result_node[7]                                              ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|result_node[8]                                                    ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|result_node[8]                                              ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|result_node[9]                                                    ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|result_node[9]                                              ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]~0                                 ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]~0                           ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]                                   ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]                             ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~0                                                 ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~0                                           ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~3                                                 ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~3                                           ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[9]~1                                 ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[9]~1                           ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[8]~2                                 ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[8]~2                           ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7]~3                                 ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7]~3                           ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[6]~4                                 ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[6]~4                           ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[5]~5                                 ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[5]~5                           ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[4]~6                                 ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[4]~6                           ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]~7                                 ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]~7                           ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]~8                                 ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]~8                           ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]~9                                 ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]~9                           ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[9]                                   ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[9]                             ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[8]                                   ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[8]                             ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7]                                   ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7]                             ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[6]                                   ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[6]                             ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[5]                                   ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[5]                             ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[4]                                   ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[4]                             ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]                                   ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]                             ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]                                   ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]                             ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]                                   ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]                             ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~13                                                ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~13                                          ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~14                                                ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~14                                          ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~15                                                ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~15                                          ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~16                                                ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~16                                          ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~17                                                ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~17                                          ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~18                                                ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~18                                          ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~19                                                ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~19                                          ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~20                                                ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~20                                          ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~21                                                ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~21                                          ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~22                                                ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~22                                          ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~23                                                ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~23                                          ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~24                                                ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~24                                          ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~25                                                ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~25                                          ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~26                                                ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~26                                          ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~27                                                ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~27                                          ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~28                                                ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~28                                          ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~29                                                ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~29                                          ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~30                                                ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~30                                          ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~31                                                ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~31                                          ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~32                                                ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~32                                          ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~33                                                ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~33                                          ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~34                                                ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~34                                          ; out0             ;
; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~35                                                ; |FPGA_AM_TEST|BU_MA:inst|lpm_add_sub:Add0|addcore:adder|_~35                                          ; out0             ;