fpga_am.sim.rpt

基于cyclone系列FPGA的模拟幅度调制的VHDL代码

; Group bus channels in simulation results                                                   ; Off                ; Off           ;
; Preserve fewer signal transitions to reduce memory requirements                            ; On                 ; On            ;
; Trigger vector comparison with the specified mode                                          ; INPUT_EDGE         ; INPUT_EDGE    ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off                ; Off           ;
; Overwrite Waveform Inputs With Simulation Outputs                                          ; On                 ;               ;
; Perform Glitch Filtering in Timing Simulation                                              ; Auto               ; Auto          ;
+--------------------------------------------------------------------------------------------+--------------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+-----------------------------------------------------------------------------------------------------------+
; |FPGA_AM_TEST|CARRIER_ROM:inst1|altsyncram:altsyncram_component|altsyncram_u981:auto_generated|ALTSYNCRAM ;
+-----------------------------------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      81.96 % ;
; Total nodes checked                                 ; 237          ;
; Total output ports checked                          ; 255          ;
; Total output ports with complete 1/0-value coverage ; 209          ;
; Total output ports with no 1/0-value coverage       ; 46           ;
; Total output ports with no 1-value coverage         ; 46           ;
; Total output ports with no 0-value coverage         ; 46           ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                                                            ;
+-------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                                   ; Output Port Name                                                                                      ; Output Port Type ;
+-------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------+------------------+
; |FPGA_AM_TEST|DATA_OUT[21]                                                                                  ; |FPGA_AM_TEST|DATA_OUT[21]                                                                            ; pin_out          ;
; |FPGA_AM_TEST|DATA_OUT[20]                                                                                  ; |FPGA_AM_TEST|DATA_OUT[20]                                                                            ; pin_out          ;
; |FPGA_AM_TEST|DATA_OUT[19]                                                                                  ; |FPGA_AM_TEST|DATA_OUT[19]                                                                            ; pin_out          ;
; |FPGA_AM_TEST|DATA_OUT[18]                                                                                  ; |FPGA_AM_TEST|DATA_OUT[18]                                                                            ; pin_out          ;
; |FPGA_AM_TEST|DATA_OUT[17]                                                                                  ; |FPGA_AM_TEST|DATA_OUT[17]                                                                            ; pin_out          ;
; |FPGA_AM_TEST|DATA_OUT[16]                                                                                  ; |FPGA_AM_TEST|DATA_OUT[16]                                                                            ; pin_out          ;
; |FPGA_AM_TEST|DATA_OUT[15]                                                                                  ; |FPGA_AM_TEST|DATA_OUT[15]                                                                            ; pin_out          ;
; |FPGA_AM_TEST|DATA_OUT[14]                                                                                  ; |FPGA_AM_TEST|DATA_OUT[14]                                                                            ; pin_out          ;
; |FPGA_AM_TEST|DATA_OUT[13]                                                                                  ; |FPGA_AM_TEST|DATA_OUT[13]                                                                            ; pin_out          ;
; |FPGA_AM_TEST|DATA_OUT[12]                                                                                  ; |FPGA_AM_TEST|DATA_OUT[12]                                                                            ; pin_out          ;
; |FPGA_AM_TEST|DATA_OUT[11]                                                                                  ; |FPGA_AM_TEST|DATA_OUT[11]                                                                            ; pin_out          ;
; |FPGA_AM_TEST|DATA_OUT[10]                                                                                  ; |FPGA_AM_TEST|DATA_OUT[10]                                                                            ; pin_out          ;
; |FPGA_AM_TEST|DATA_OUT[9]                                                                                   ; |FPGA_AM_TEST|DATA_OUT[9]                                                                             ; pin_out          ;
; |FPGA_AM_TEST|DATA_OUT[8]                                                                                   ; |FPGA_AM_TEST|DATA_OUT[8]                                                                             ; pin_out          ;
; |FPGA_AM_TEST|DATA_OUT[7]                                                                                   ; |FPGA_AM_TEST|DATA_OUT[7]                                                                             ; pin_out          ;
; |FPGA_AM_TEST|DATA_OUT[6]                                                                                   ; |FPGA_AM_TEST|DATA_OUT[6]                                                                             ; pin_out          ;
; |FPGA_AM_TEST|DATA_OUT[5]                                                                                   ; |FPGA_AM_TEST|DATA_OUT[5]                                                                             ; pin_out          ;
; |FPGA_AM_TEST|DATA_OUT[4]                                                                                   ; |FPGA_AM_TEST|DATA_OUT[4]                                                                             ; pin_out          ;
; |FPGA_AM_TEST|DATA_OUT[3]                                                                                   ; |FPGA_AM_TEST|DATA_OUT[3]                                                                             ; pin_out          ;
; |FPGA_AM_TEST|DATA_OUT[2]                                                                                   ; |FPGA_AM_TEST|DATA_OUT[2]                                                                             ; pin_out          ;
; |FPGA_AM_TEST|DATA_OUT[1]                                                                                   ; |FPGA_AM_TEST|DATA_OUT[1]                                                                             ; pin_out          ;
; |FPGA_AM_TEST|DATA_OUT[0]                                                                                   ; |FPGA_AM_TEST|DATA_OUT[0]                                                                             ; pin_out          ;
; |FPGA_AM_TEST|LCK                                                                                           ; |FPGA_AM_TEST|LCK                                                                                     ; out              ;
; |FPGA_AM_TEST|CARRIER:inst2|PHASE_WORD[0]                                                                   ; |FPGA_AM_TEST|CARRIER:inst2|PHASE_WORD[0]                                                             ; regout           ;
; |FPGA_AM_TEST|CARRIER:inst2|PHASE_WORD[1]                                                                   ; |FPGA_AM_TEST|CARRIER:inst2|PHASE_WORD[1]                                                             ; regout           ;
; |FPGA_AM_TEST|CARRIER:inst2|PHASE_WORD[2]                                                                   ; |FPGA_AM_TEST|CARRIER:inst2|PHASE_WORD[2]                                                             ; regout           ;
; |FPGA_AM_TEST|CARRIER:inst2|PHASE_WORD[3]                                                                   ; |FPGA_AM_TEST|CARRIER:inst2|PHASE_WORD[3]                                                             ; regout           ;
; |FPGA_AM_TEST|CARRIER:inst2|PHASE_WORD[4]                                                                   ; |FPGA_AM_TEST|CARRIER:inst2|PHASE_WORD[4]                                                             ; regout           ;
; |FPGA_AM_TEST|CARRIER:inst2|PHASE_WORD[5]                                                                   ; |FPGA_AM_TEST|CARRIER:inst2|PHASE_WORD[5]                                                             ; regout           ;
; |FPGA_AM_TEST|CARRIER:inst2|PHASE_WORD[6]                                                                   ; |FPGA_AM_TEST|CARRIER:inst2|PHASE_WORD[6]                                                             ; regout           ;
; |FPGA_AM_TEST|CARRIER:inst2|PHASE_WORD[7]                                                                   ; |FPGA_AM_TEST|CARRIER:inst2|PHASE_WORD[7]                                                             ; regout           ;
; |FPGA_AM_TEST|CARRIER:inst2|PHASE_WORD[8]                                                                   ; |FPGA_AM_TEST|CARRIER:inst2|PHASE_WORD[8]                                                             ; regout           ;