fpga_am.fit.rpt

基于cyclone系列FPGA的模拟幅度调制的VHDL代码

; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;
; Final Placement Optimizations                                      ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                        ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                      ; 1                              ; 1                              ;
; Slow Slew Rate                                                     ; Off                            ; Off                            ;
; PCI I/O                                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                 ; Off                            ; Off                            ;
; Auto Packed Registers -- Cyclone                                   ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                  ; On                             ; On                             ;
; Auto Merge PLLs                                                    ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
; Fitter Effort                                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication                           ; Auto                           ; Auto                           ;
; Auto Register Duplication                                          ; Auto                           ; Auto                           ;
; Auto Global Clock                                                  ; On                             ; On                             ;
; Auto Global Register Control Signals                               ; On                             ; On                             ;
; Stop After Congestion Map Generation                               ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                  ; Off                            ; Off                            ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations                                                                                                                                                                                                                       ;
+------------------------------------------------------------------------------------------------------+---------+------------------+---------------------+-----------+----------------+------------------+------------------+-----------------------+
; Node                                                                                                 ; Action  ; Operation        ; Reason              ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ;
+------------------------------------------------------------------------------------------------------+---------+------------------+---------------------+-----------+----------------+------------------+------------------+-----------------------+
; FI_OUT:inst15|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[9]~1 ; Deleted ; Register Packing ; Timing optimization ; COMBOUT   ;                ;                  ;                  ;                       ;
+------------------------------------------------------------------------------------------------------+---------+------------------+---------------------+-----------+----------------+------------------+------------------+-----------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in J:/FPGA/my_exercises/AM/project/FPGA_AM.pin.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                                                                                                             ;
+---------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+
; Resource                                    ; Usage                                                                                                                       ;
+---------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+
; Total logic elements                        ; 280 / 2,910 ( 10 % )                                                                                                        ;
;     -- Combinational with no register       ; 253                                                                                                                         ;
;     -- Register only                        ; 8                                                                                                                           ;
;     -- Combinational with a register        ; 19                                                                                                                          ;
;                                             ;                                                                                                                             ;
; Logic element usage by number of LUT inputs ;                                                                                                                             ;
;     -- 4 input functions                    ; 75                                                                                                                          ;
;     -- 3 input functions                    ; 115                                                                                                                         ;
;     -- 2 input functions                    ; 58                                                                                                                          ;
;     -- 1 input functions                    ; 29                                                                                                                          ;
;     -- 0 input functions                    ; 3                                                                                                                           ;
;                                             ;                                                                                                                             ;
; Logic elements by mode                      ;                                                                                                                             ;
;     -- normal mode                          ; 129                                                                                                                         ;
;     -- arithmetic mode                      ; 151                                                                                                                         ;
;     -- qfbk mode                            ; 2                                                                                                                           ;
;     -- register cascade mode                ; 0                                                                                                                           ;
;     -- synchronous clear/load mode          ; 5                                                                                                                           ;
;     -- asynchronous clear/load mode         ; 0                                                                                                                           ;
;                                             ;                                                                                                                             ;
; Total registers                             ; 27 / 3,210 ( < 1 % )                                                                                                        ;
; Total LABs                                  ; 31 / 291 ( 11 % )                                                                                                           ;
; Logic elements in carry chains              ; 167                                                                                                                         ;
; User inserted logic elements                ; 0                                                                                                                           ;
; Virtual pins                                ; 0                                                                                                                           ;
; I/O pins                                    ; 13 / 104 ( 13 % )                                                                                                           ;
;     -- Clock pins                           ; 1 / 2 ( 50 % )                                                                                                              ;
; Global signals                              ; 2                                                                                                                           ;
; M4Ks                                        ; 5 / 13 ( 38 % )                                                                                                             ;
; Total memory bits                           ; 14,180 / 59,904 ( 24 % )                                                                                                    ;
; Total RAM block bits                        ; 23,040 / 59,904 ( 38 % )                                                                                                    ;
; PLLs                                        ; 1 / 1 ( 100 % )                                                                                                             ;
; Global clocks                               ; 2 / 8 ( 25 % )                                                                                                              ;
; Average interconnect usage                  ; 3%                                                                                                                          ;
; Peak interconnect usage                     ; 3%                                                                                                                          ;
; Maximum fan-out node                        ; lpm_rom0_394:inst9|altsyncram:altsyncram_component|lpm_rom0_394_altsyncram:auto_generated|wire_ram_block1a_9portadataout[0] ;
; Maximum fan-out                             ; 59                                                                                                                          ;
; Highest non-global fan-out signal           ; ADD256:inst12|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[9]~8                        ;
; Highest non-global fan-out                  ; 23                                                                                                                          ;
; Total fan-out                               ; 929                                                                                                                         ;
; Average fan-out                             ; 3.09                                                                                                                        ;
+---------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                     ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;