test.vhd

来自「基于cyclone系列FPGA的模拟幅度调制的VHDL代码」· VHDL 代码 · 共 26 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
USE IEEE.STD_LOGIC_ARITH.ALL ;
ENTITY TEST IS
PORT( CLK: IN STD_LOGIC ;
      CLK_OUT :BUFFER STD_LOGIC );
END ENTITY ;

ARCHITECTURE BUILDING OF TEST IS
BEGIN
TESTING : PROCESS(CLK)
          VARIABLE COUNT : INTEGER RANGE 0 TO 50000 ;
          BEGIN
            IF(CLK'EVENT AND CLK = '1') THEN
              COUNT := COUNT + 1 ;
              IF(COUNT = 33333) THEN
                COUNT := 0 ;
                CLK_OUT <= NOT CLK_OUT ;
                END IF ;
            END IF ;
          END PROCESS ;
END  ARCHITECTURE ;