carrier_khz507.vhd

来自「基于cyclone系列FPGA的模拟幅度调制的VHDL代码」· VHDL 代码 · 共 39 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
USE IEEE.STD_LOGIC_ARITH.ALL ;

ENTITY CARRIER_507 IS
PORT( 
      CLK : IN STD_LOGIC ;
      
      DDS_ADDR : OUT  STD_LOGIC_VECTOR(8 DOWNTO 0) ) ;
END ENTITY CARRIER_507 ;

ARCHITECTURE BUILDING OF CARRIER_507 IS
SIGNAL PHASE_WORD : STD_LOGIC_VECTOR(8 DOWNTO 0)  ;
BEGIN 
 
  DDS : PROCESS(CLK) 
          
          BEGIN
           IF(CLK'EVENT AND CLK = '1') THEN
             PHASE_WORD <= PHASE_WORD + '1' ;
              IF(PHASE_WORD = "110001001") THEN
                PHASE_WORD <= "000000000";
              END IF ;
           END IF ; 
        END PROCESS ;     
        DDS_ADDR <= PHASE_WORD ;    
          
          
      
  
        
END ARCHITECTURE BUILDING  ;