modem.vhd

基于cyclone系列FPGA的模拟幅度调制的VHDL代码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
USE IEEE.STD_LOGIC_ARITH.ALL ;

ENTITY MODEM IS
PORT( CLK : IN STD_LOGIC ;
      FSK_DATA : IN STD_LOGIC ;
      --CLK_50M : IN STD_LOGIC ;
      --CLK_DA : OUT STD_LOGIC ; 
      DDS_ADDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ) ;
END ENTITY MODEM ;

ARCHITECTURE BUILDING OF MODEM IS
SIGNAL PHASE_WORD : STD_LOGIC_VECTOR(9 DOWNTO 0)  ;
BEGIN 
  --KEY_WORD <= "0000000100" ;
  --CLK_DA <= CLK ;
   
  DDS : PROCESS(CLK ,FSK_DATA) 
        VARIABLE COUNT : INTEGER RANGE 0 TO 240;
        BEGIN
          IF(CLK'EVENT AND CLK = '1') THEN
            COUNT := COUNT + 1 ;
            IF(COUNT = 200) THEN
              COUNT := 0 ;
              IF(FSK_DATA = '0') THEN
                PHASE_WORD <= PHASE_WORD + "0000000101" ;
               --PHASE_WORD <= PHASE_WORD + "0000011001" ;
              ELSIF(FSK_DATA = '1') THEN 
                PHASE_WORD <= PHASE_WORD + "0000010001" ;
                 --PHASE_WORD <= PHASE_WORD + "0000000000" ;
              END IF ;
            END IF ; 
           END IF ;
          
        END PROCESS DDS ;
  DDS_ADDR <= PHASE_WORD ;
        
END ARCHITECTURE BUILDING  ;