fpga_am.tan.rpt

基于cyclone系列FPGA的模拟幅度调制的VHDL代码

; Worst-case tsu                                                  ; N/A       ; None                             ; 6.160 ns                                       ; fsk_data                                                                                                         ; MODEM:inst4|PHASE_WORD[9]        ; --                                               ; LCK                                              ; 0            ;
; Worst-case tco                                                  ; N/A       ; None                             ; 38.583 ns                                      ; CARRIER_ROM:inst3|altsyncram:altsyncram_component|altsyncram_u981:auto_generated|ram_block1a1~porta_address_reg9 ; RESULT[6]                        ; LCK                                              ; --                                               ; 0            ;
; Worst-case tpd                                                  ; N/A       ; None                             ; 5.013 ns                                       ; LCK                                                                                                              ; DA_CLK                           ; --                                               ; --                                               ; 0            ;
; Worst-case th                                                   ; N/A       ; None                             ; -5.134 ns                                      ; fsk_data                                                                                                         ; MODEM:inst4|PHASE_WORD[2]        ; --                                               ; LCK                                              ; 0            ;
; Clock Setup: 'altpll0_200M:inst6|altpll:altpll_component|_clk0' ; 1.413 ns  ; 200.00 MHz ( period = 5.000 ns ) ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CARRIER_507:inst16|PHASE_WORD[1]                                                                                 ; CARRIER_507:inst16|PHASE_WORD[7] ; altpll0_200M:inst6|altpll:altpll_component|_clk0 ; altpll0_200M:inst6|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'LCK'                                              ; 12.126 ns ; 50.00 MHz ( period = 20.000 ns ) ; 127.00 MHz ( period = 7.874 ns )               ; MODEM:inst4|\DDS:COUNT[0]                                                                                        ; MODEM:inst4|PHASE_WORD[9]        ; LCK                                              ; LCK                                              ; 0            ;
; Clock Hold: 'altpll0_200M:inst6|altpll:altpll_component|_clk0'  ; 1.078 ns  ; 200.00 MHz ( period = 5.000 ns ) ; N/A                                            ; CARRIER_507:inst16|PHASE_WORD[4]                                                                                 ; CARRIER_507:inst16|PHASE_WORD[7] ; altpll0_200M:inst6|altpll:altpll_component|_clk0 ; altpll0_200M:inst6|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'LCK'                                               ; 1.323 ns  ; 50.00 MHz ( period = 20.000 ns ) ; N/A                                            ; MODEM:inst4|PHASE_WORD[8]                                                                                        ; MODEM:inst4|PHASE_WORD[8]        ; LCK                                              ; LCK                                              ; 0            ;
; Total number of failed paths                                    ;           ;                                  ;                                                ;                                                                                                                  ;                                  ;                                                  ;                                                  ; 0            ;
+-----------------------------------------------------------------+-----------+----------------------------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------------+----------------------------------+--------------------------------------------------+--------------------------------------------------+--------------+


+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                      ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                         ; Setting            ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; Off                ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                                   ;
+--------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                                  ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+--------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; altpll0_200M:inst6|altpll:altpll_component|_clk0 ;                    ; PLL output ; 200.0 MHz        ; 0.000 ns      ; 0.000 ns     ; LCK      ; 4                     ; 1                   ; -1.833 ns ;              ;
; LCK                                              ;                    ; User Pin   ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+--------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+