fpga_am.tan.summary

基于cyclone系列FPGA的模拟幅度调制的VHDL代码

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.160 ns
From           : fsk_data
To             : MODEM:inst4|PHASE_WORD[9]
From Clock     : --
To Clock       : LCK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 38.583 ns
From           : CARRIER_ROM:inst3|altsyncram:altsyncram_component|altsyncram_u981:auto_generated|ram_block1a1~porta_address_reg9
To             : RESULT[6]
From Clock     : LCK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 5.013 ns
From           : LCK
To             : DA_CLK
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -5.134 ns
From           : fsk_data
To             : MODEM:inst4|PHASE_WORD[2]
From Clock     : --
To Clock       : LCK
Failed Paths   : 0

Type           : Clock Setup: 'altpll0_200M:inst6|altpll:altpll_component|_clk0'
Slack          : 1.413 ns
Required Time  : 200.00 MHz ( period = 5.000 ns )
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : CARRIER_507:inst16|PHASE_WORD[1]
To             : CARRIER_507:inst16|PHASE_WORD[7]
From Clock     : altpll0_200M:inst6|altpll:altpll_component|_clk0
To Clock       : altpll0_200M:inst6|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'LCK'
Slack          : 12.126 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : 127.00 MHz ( period = 7.874 ns )
From           : MODEM:inst4|\DDS:COUNT[0]
To             : MODEM:inst4|PHASE_WORD[9]
From Clock     : LCK
To Clock       : LCK
Failed Paths   : 0

Type           : Clock Hold: 'altpll0_200M:inst6|altpll:altpll_component|_clk0'
Slack          : 1.078 ns
Required Time  : 200.00 MHz ( period = 5.000 ns )
Actual Time    : N/A
From           : CARRIER_507:inst16|PHASE_WORD[4]
To             : CARRIER_507:inst16|PHASE_WORD[7]
From Clock     : altpll0_200M:inst6|altpll:altpll_component|_clk0
To Clock       : altpll0_200M:inst6|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'LCK'
Slack          : 1.323 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : MODEM:inst4|PHASE_WORD[8]
To             : MODEM:inst4|PHASE_WORD[8]
From Clock     : LCK
To Clock       : LCK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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