ide_ext.tim

非常优秀的CPLD源代码

                           Performance Summary Report
                           --------------------------

Design:     IDE_EXT
Device:     XC9572XL-10-VQ64
Speed File: Version 3.0
Program:    Timing Report Generator:  version G.23
Date:       Fri Apr 29 10:02:44 2005

Performance Summary:

Pad to Pad (tPD)                          :         11.0ns (1 macrocell levels)
Pad 'NRD' to Pad 'DATA<0>'                                        

--------------------------------------------------------------------------------
                            Pad to Pad (tPD) (nsec)

\ From           A     A     A     A     A     I     I     N     N     N     N
 \               D     D     D     D     D     D     O     C     C     C     R
  \              D     D     D     D     D     E     _     S     S     S     D
   \             R     R     R     R     R     _     I     2     3     4      
    \            2     3     4     5     6     I     D                        
     \                                         N     E                        
      \                                        T     _                        
       \                                             I                        
        \                                            N                        
         \                                           T                        
          \                                                                   
           \                                                                  
  To        \------------------------------------------------------------------

BUF_DIR                                                                   10.0
BUF_OE                                                  10.0  10.0  10.0      
DATA<0>                                                             11.0  11.0
DATA<1>                                                             11.0  11.0
DATA<2>                                                             11.0  11.0
DATA<3>                                                             11.0  11.0
DATA<4>                                                             11.0  11.0
DATA<5>                                                             11.0  11.0
DATA<6>                                                             11.0  11.0
DATA<7>                                                             11.0  11.0
IDE_CS0                         10.0                                          
IDE_CS1                               10.0                                    
IDE_DA<0>     10.0                                                            
IDE_DA<1>           10.0                                                      
IDE_DA<2>                 10.0                                                
IDE_IOR                                                 10.0              10.0
IDE_IOW                                                 10.0                  
IDE_RST                                                                       
IO_IDE_CS0                      10.0                                          
IO_IDE_CS1                            10.0                                    
IO_IDE_DA<0>  10.0                                                            
IO_IDE_DA<1>        10.0                                                      
IO_IDE_DA<2>              10.0                                                
IO_IDE_IOR                                                    10.0        10.0
IO_IDE_IOW                                                    10.0            
IO_IDE_RST                                                                    
IRQ0                                        10.0                              
IRQ3                                              10.0                        

--------------------------------------------------------------------------------
                            Pad to Pad (tPD) (nsec)

\ From           N     N
 \               R     W
  \              S     E
   \             T      
    \                   
     \                  
      \                 
       \                
        \               
         \              
          \             
           \            
  To        \------------

BUF_DIR                 
BUF_OE                  
DATA<0>                 
DATA<1>                 
DATA<2>                 
DATA<3>                 
DATA<4>                 
DATA<5>                 
DATA<6>                 
DATA<7>                 
IDE_CS0                 
IDE_CS1                 
IDE_DA<0>               
IDE_DA<1>               
IDE_DA<2>               
IDE_IOR                 
IDE_IOW             10.0
IDE_RST       10.0      
IO_IDE_CS0              
IO_IDE_CS1              
IO_IDE_DA<0>            
IO_IDE_DA<1>            
IO_IDE_DA<2>            
IO_IDE_IOR              
IO_IDE_IOW          10.0
IO_IDE_RST    10.0      
IRQ0                    
IRQ3                    

Path Type Definition: 

Pad to Pad (tPD) -                        Reports pad to pad paths that start 
                                          at input pads and end at output pads. 
                                          Paths are not traced through 
                                          registers. 

Clock Pad to Output Pad (tCO) -           Reports paths that start at input 
                                          pads trace through clock inputs of 
                                          registers and end at output pads. 
                                          Paths are not traced through PRE/CLR 
                                          inputs of registers. 

Setup to Clock at Pad (tSU or tSUF) -     Reports external setup time of data 
                                          to clock at pad. Data path starts at 
                                          an input pad and ends at register 
                                          (Fast Input Register for tSUF) D/T 
                                          input. Clock path starts at input pad 
                                          and ends at the register clock input. 
                                          Paths are not traced through 
                                          registers. Pin-to-pin setup 
                                          requirement is not reported or 
                                          guaranteed for product-term clocks 
                                          derived from macrocell feedback 
                                          signals. 

Clock to Setup (tCYC) -                   Register to register cycle time. 
                                          Include source register tCO and 
                                          destination register tSU. Note that 
                                          when the computed Maximum Clock Speed 
                                          is limited by tCYC it is computed 
                                          assuming that all registers are 
                                          rising-edge sensitive.