ide_ext.syr

非常优秀的CPLD源代码

Release 6.1i - xst G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.19 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.19 s | Elapsed : 0.00 / 0.00 s
 
--> Reading design: IDE_EXT.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
  6) Low Level Synthesis
  7) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : IDE_EXT.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : IDE_EXT
Output Format                      : NGC
Target Device                      : xc9500xl

---- Source Options
Top Module Name                    : IDE_EXT
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : YES
RTL Output                         : Yes
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain

---- Other Options
lso                                : IDE_EXT.lso
verilog2001                        : YES
Clock Enable                       : YES
wysiwyg                            : NO

=========================================================================

WARNING:Xst:1885 - LSO file is empty, default list of libraries is used

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "IDE_EXT.v"
Module <IDE_EXT> compiled
No errors in compilation
Analysis of file <IDE_EXT.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <IDE_EXT>.
WARNING:Xst:863 - IDE_EXT.v line 14: Name conflict (<data> and <DATA>, renaming data as data_rnm0).
WARNING:Xst:905 - IDE_EXT.v line 34: The signals <DATA> are missing in the sensitivity list of always block.
Module <IDE_EXT> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <IDE_EXT>.
    Related source file is IDE_EXT.v.
WARNING:Xst:647 - Input <IDE_IORDY> is never used.
WARNING:Xst:1306 - Output <SPCK> is never assigned.
WARNING:Xst:1306 - Output <TIOA1> is never assigned.
WARNING:Xst:1306 - Output <NPCS0> is never assigned.
WARNING:Xst:1306 - Output <TWD> is never assigned.
WARNING:Xst:1306 - Output <MOSI> is never assigned.
WARNING:Xst:647 - Input <IO_IDE_IORDY> is never used.
WARNING:Xst:1306 - Output <PCK0> is never assigned.
WARNING:Xst:1306 - Output <TWCK> is never assigned.
WARNING:Xst:1306 - Output <MISO> is never assigned.
WARNING:Xst:737 - Found 8-bit latch for signal <data_rnm0>.
    Found 8-bit tristate buffer for signal <DATA>.
    Summary:
	inferred   8 Tristate(s).
Unit <IDE_EXT> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Latches                          : 1
  8-bit latch                      : 1
# Tristates                        : 1
  8-bit tristate buffer            : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <IDE_EXT> ...

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : IDE_EXT.ngr
Top Level Output File Name         : IDE_EXT
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : YES
Target Technology                  : xc9500xl
Macro Preserve                     : YES
XOR Preserve                       : YES
Clock Enable                       : YES
wysiwyg                            : NO

Design Statistics
# IOs                              : 52

Macro Statistics :
# Tristates                        : 1
#      8-bit tristate buffer       : 1

Cell Usage :
# BELS                             : 24
#      AND2                        : 6
#      AND3                        : 1
#      INV                         : 16
#      VCC                         : 1
# FlipFlops/Latches                : 8
#      LD                          : 8
# IO Buffers                       : 42
#      IBUF                        : 13
#      IOBUFE                      : 8
#      OBUF                        : 21
=========================================================================
CPU : 0.55 / 0.83 s | Elapsed : 1.00 / 1.00 s
 
--> 

Total memory usage is 48944 kilobytes