📄 ide_ext.rpt
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Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 13/41
Number of signals used by logic mapping into function block: 13
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB4_1 (b)
(unused) 0 0 0 5 FB4_2 43 I/O I
DATA<2> 3 0 0 2 FB4_3 STD 46 I/O I/O
DATA<3> 3 0 0 2 FB4_4 STD 47 I/O I/O
DATA<0> 3 0 0 2 FB4_5 STD 44 I/O I/O
DATA<5> 3 0 0 2 FB4_6 STD 49 I/O I/O
(unused) 0 0 0 5 FB4_7 (b)
DATA<1> 3 0 0 2 FB4_8 STD 45 I/O I/O
(unused) 0 0 0 5 FB4_9 (b)
DATA<7> 3 0 0 2 FB4_10 STD 51 I/O I/O
DATA<4> 3 0 0 2 FB4_11 STD 48 I/O I/O
IRQ0 1 0 0 4 FB4_12 STD 52 I/O O
(unused) 0 0 0 5 FB4_13 (b)
DATA<6> 3 0 0 2 FB4_14 STD 50 I/O I/O
IRQ3 1 0 0 4 FB4_15 STD 56 I/O O
(unused) 0 0 0 5 FB4_16 (b)
NWAIT 0 0 0 5 FB4_17 STD 57 I/O O
(unused) 0 0 0 5 FB4_18 (b)
Signals Used by Logic in Function Block
1: NRD 6: DATA<2>.PIN 10: DATA<6>.PIN
2: IDE_INT 7: DATA<3>.PIN 11: DATA<7>.PIN
3: IO_IDE_INT 8: DATA<4>.PIN 12: NCS4
4: DATA<0>.PIN 9: DATA<5>.PIN 13: NWE
5: DATA<1>.PIN
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
DATA<2> X....X.....XX........................... 4 4
DATA<3> X.....X....XX........................... 4 4
DATA<0> X..X.......XX........................... 4 4
DATA<5> X.......X..XX........................... 4 4
DATA<1> X...X......XX........................... 4 4
DATA<7> X.........XXX........................... 4 4
DATA<4> X......X...XX........................... 4 4
IRQ0 .X...................................... 1 1
DATA<6> X........X.XX........................... 4 4
IRQ3 ..X..................................... 1 1
NWAIT ........................................ 0 0
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
BUF_DIR = NRD;
BUF_OE = NCS4 & NCS3 & NCS2;
IO_IDE_DA<0> = ADDR2;
IDE_DA<0> = ADDR2;
IO_IDE_DA<1> = ADDR3;
IDE_DA<1> = ADDR3;
IO_IDE_DA<2> = ADDR4;
IDE_DA<2> = ADDR4;
!IDE_IOR = !NCS2 & !NRD;
!IDE_IOW = !NCS2 & !NWE;
IO_IDE_CS0 = ADDR5;
IDE_CS0 = ADDR5;
IO_IDE_CS1 = ADDR6;
IDE_CS1 = ADDR6;
!IO_IDE_IOR = !NCS3 & !NRD;
!IO_IDE_IOW = !NCS3 & !NWE;
IO_IDE_RST = NRST;
IDE_RST = NRST;
IRQ0 = IDE_INT;
IRQ3 = IO_IDE_INT;
NWAIT = Vcc;
DATA<0>.D = Gnd;
DATA<0>.CLK = Gnd;
DATA<0>.AP = !NCS4 & !NWE & DATA<0>.PIN;
DATA<0>.AR = !NCS4 & !NWE & !DATA<0>.PIN;
DATA<0>.OE = !NCS4 & !NRD;
DATA<1>.D = Gnd;
DATA<1>.CLK = Gnd;
DATA<1>.AP = !NCS4 & !NWE & DATA<1>.PIN;
DATA<1>.AR = !NCS4 & !NWE & !DATA<1>.PIN;
DATA<1>.OE = !NCS4 & !NRD;
DATA<2>.D = Gnd;
DATA<2>.CLK = Gnd;
DATA<2>.AP = !NCS4 & !NWE & DATA<2>.PIN;
DATA<2>.AR = !NCS4 & !NWE & !DATA<2>.PIN;
DATA<2>.OE = !NCS4 & !NRD;
DATA<3>.D = Gnd;
DATA<3>.CLK = Gnd;
DATA<3>.AP = !NCS4 & !NWE & DATA<3>.PIN;
DATA<3>.AR = !NCS4 & !NWE & !DATA<3>.PIN;
DATA<3>.OE = !NCS4 & !NRD;
DATA<4>.D = Gnd;
DATA<4>.CLK = Gnd;
DATA<4>.AP = !NCS4 & !NWE & DATA<4>.PIN;
DATA<4>.AR = !NCS4 & !NWE & !DATA<4>.PIN;
DATA<4>.OE = !NCS4 & !NRD;
DATA<5>.D = Gnd;
DATA<5>.CLK = Gnd;
DATA<5>.AP = !NCS4 & !NWE & DATA<5>.PIN;
DATA<5>.AR = !NCS4 & !NWE & !DATA<5>.PIN;
DATA<5>.OE = !NCS4 & !NRD;
DATA<6>.D = Gnd;
DATA<6>.CLK = Gnd;
DATA<6>.AP = !NCS4 & !NWE & DATA<6>.PIN;
DATA<6>.AR = !NCS4 & !NWE & !DATA<6>.PIN;
DATA<6>.OE = !NCS4 & !NRD;
DATA<7>.D = Gnd;
DATA<7>.CLK = Gnd;
DATA<7>.AP = !NCS4 & !NWE & DATA<7>.PIN;
DATA<7>.AR = !NCS4 & !NWE & !DATA<7>.PIN;
DATA<7>.OE = !NCS4 & !NRD;
Legend: <signame>.COMB = combinational node mapped to the same physical macrocell
as the FastInput "signal" (not logically related)
**************************** Device Pin Out ****************************
Device : XC9572XL-10-VQ64
-----------------------------------------------
/48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 \
| 49 32 |
| 50 31 |
| 51 30 |
| 52 29 |
| 53 28 |
| 54 27 |
| 55 26 |
| 56 XC9572XL-10-VQ64 25 |
| 57 24 |
| 58 23 |
| 59 22 |
| 60 21 |
| 61 20 |
| 62 19 |
| 63 18 |
| 64 17 |
\ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 /
-----------------------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 IDE_CS0 33 BUF_OE
2 IDE_RST 34 TIE
3 VCC 35 TIE
4 IDE_CS1 36 TIE
5 IDE_IOW 37 VCC
6 IDE_IOR 38 TIE
7 TIE 39 TIE
8 IDE_DA<0> 40 TIE
9 IDE_DA<1> 41 GND
10 IDE_DA<2> 42 TIE
11 IO_IDE_DA<0> 43 IO_IDE_INT
12 IO_IDE_DA<1> 44 DATA<0>
13 IO_IDE_DA<2> 45 DATA<1>
14 GND 46 DATA<2>
15 IO_IDE_CS0 47 DATA<3>
16 IO_IDE_CS1 48 DATA<4>
17 TIE 49 DATA<5>
18 IO_IDE_IOW 50 DATA<6>
19 IO_IDE_IOR 51 DATA<7>
20 IO_IDE_RST 52 IRQ0
21 GND 53 TDO
22 ADDR2 54 GND
23 TIE 55 VCC
24 ADDR3 56 IRQ3
25 ADDR4 57 NWAIT
26 VCC 58 IDE_INT
27 ADDR5 59 NCS2
28 TDI 60 NCS3
29 TMS 61 NCS4
30 TCK 62 NRD
31 ADDR6 63 NWE
32 BUF_DIR 64 NRST
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PE = Port Enable pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc9572xl-10-VQ64
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Set Unused I/O Pin Termination : FLOAT
Set I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 54
Pterm Limit : 25
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