📄 ide_ext.rpt
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cpldfit: version G.23 Xilinx Inc.
Fitter Report
Design Name: IDE_EXT Date: 4-29-2005, 10:02AM
Device Used: XC9572XL-10-VQ64
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
29 /72 ( 40%) 44 /360 ( 12%) 8 /72 ( 11%) 42 /52 ( 81%) 32 /216 ( 15%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 13 13 | I/O : 37 9
Output : 21 21 | GCK/IO : 2 1
Bidirectional : 8 8 | GTS/IO : 2 0
GCK : 0 0 | GSR/IO : 1 0
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 42 42
MACROCELL RESOURCES:
Total Macrocells Available 72
Registered Macrocells 8
Non-registered Macrocell driving I/O 21
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 29 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 29 macrocells used (MC).
End of Resource Summary
**************************** Errors and Warnings *************************
WARNING:Cpld:1007 - Removing unused input(s) 'IDE_IORDY'. The input(s) are
unused after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'IO_IDE_IORDY'. The input(s) are
unused after optimization. Please verify functionality via simulation.
*************** Summary of Required Resources ******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init
Name Pt Used Mode Rate # Type Use State
BUF_DIR 1 1 FB3_4 STD FAST 32 I/O O
BUF_OE 1 3 FB3_11 STD FAST 33 I/O O
DATA<0> 3 4 FB4_5 STD FAST 44 I/O I/O RESET
DATA<1> 3 4 FB4_8 STD FAST 45 I/O I/O RESET
DATA<2> 3 4 FB4_3 STD FAST 46 I/O I/O RESET
DATA<3> 3 4 FB4_4 STD FAST 47 I/O I/O RESET
DATA<4> 3 4 FB4_11 STD FAST 48 I/O I/O RESET
DATA<5> 3 4 FB4_6 STD FAST 49 I/O I/O RESET
DATA<6> 3 4 FB4_14 STD FAST 50 I/O I/O RESET
DATA<7> 3 4 FB4_10 STD FAST 51 I/O I/O RESET
IDE_CS0 1 1 FB2_10 STD FAST 1 I/O O
IDE_CS1 1 1 FB2_12 STD FAST 4 I/O O
IDE_DA<0> 1 1 FB1_2 STD FAST 8 I/O O
IDE_DA<1> 1 1 FB1_5 STD FAST 9 I/O O
IDE_DA<2> 1 1 FB1_6 STD FAST 10 I/O O
IDE_IOR 1 2 FB2_15 STD FAST 6 I/O O
IDE_IOW 1 2 FB2_14 STD FAST 5 GTS/I/O O
IDE_RST 1 1 FB2_11 STD FAST 2 GTS/I/O O
IO_IDE_CS0 1 1 FB1_9 STD FAST 15 GCK/I/O O
IO_IDE_CS1 1 1 FB1_11 STD FAST 16 GCK/I/O O
IO_IDE_DA<0> 1 1 FB1_8 STD FAST 11 I/O O
IO_IDE_DA<1> 1 1 FB1_3 STD FAST 12 I/O O
IO_IDE_DA<2> 1 1 FB1_4 STD FAST 13 I/O O
IO_IDE_IOR 1 2 FB1_15 STD FAST 19 I/O O
IO_IDE_IOW 1 2 FB1_10 STD FAST 18 I/O O
IO_IDE_RST 1 1 FB1_17 STD FAST 20 I/O O
IRQ0 1 1 FB4_12 STD FAST 52 I/O O
IRQ3 1 1 FB4_15 STD FAST 56 I/O O
NWAIT 0 0 FB4_17 STD FAST 57 I/O O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
ADDR2 FB3_2 22 I/O I
ADDR3 FB3_5 24 I/O I
ADDR4 FB3_8 25 I/O I
ADDR5 FB3_9 27 I/O I
ADDR6 FB3_3 31 I/O I
IDE_INT FB2_3 58 I/O I
IO_IDE_INT FB4_2 43 I/O I
NCS2 FB2_4 59 I/O I
NCS3 FB2_2 60 I/O I
NCS4 FB2_5 61 I/O I
NRD FB2_6 62 I/O I
NRST FB2_9 64 GSR/I/O I
NWE FB2_8 63 I/O I
End of Resources
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 11 9 9 11 11/0 13
FB2 5 6 6 5 5/0 13
FB3 2 4 4 2 2/0 14
FB4 11 13 13 26 3/8 12
---- ----- ----- -----
29 44 21/8 52
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 9/45
Number of signals used by logic mapping into function block: 9
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 (b)
IDE_DA<0> 1 0 0 4 FB1_2 STD 8 I/O O
IO_IDE_DA<1> 1 0 0 4 FB1_3 STD 12 I/O O
IO_IDE_DA<2> 1 0 0 4 FB1_4 STD 13 I/O O
IDE_DA<1> 1 0 0 4 FB1_5 STD 9 I/O O
IDE_DA<2> 1 0 0 4 FB1_6 STD 10 I/O O
(unused) 0 0 0 5 FB1_7 (b)
IO_IDE_DA<0> 1 0 0 4 FB1_8 STD 11 I/O O
IO_IDE_CS0 1 0 0 4 FB1_9 STD 15 GCK/I/O O
IO_IDE_IOW 1 0 0 4 FB1_10 STD 18 I/O O
IO_IDE_CS1 1 0 0 4 FB1_11 STD 16 GCK/I/O O
(unused) 0 0 0 5 FB1_12 23 I/O
(unused) 0 0 0 5 FB1_13 (b)
(unused) 0 0 0 5 FB1_14 17 GCK/I/O
IO_IDE_IOR 1 0 0 4 FB1_15 STD 19 I/O O
(unused) 0 0 0 5 FB1_16 (b)
IO_IDE_RST 1 0 0 4 FB1_17 STD 20 I/O O
(unused) 0 0 0 5 FB1_18 (b)
Signals Used by Logic in Function Block
1: NRD 4: ADDR4 7: NRST
2: ADDR2 5: ADDR5 8: NCS3
3: ADDR3 6: ADDR6 9: NWE
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
IDE_DA<0> .X...................................... 1 1
IO_IDE_DA<1> ..X..................................... 1 1
IO_IDE_DA<2> ...X.................................... 1 1
IDE_DA<1> ..X..................................... 1 1
IDE_DA<2> ...X.................................... 1 1
IO_IDE_DA<0> .X...................................... 1 1
IO_IDE_CS0 ....X................................... 1 1
IO_IDE_IOW .......XX............................... 2 2
IO_IDE_CS1 .....X.................................. 1 1
IO_IDE_IOR X......X................................ 2 2
IO_IDE_RST ......X................................. 1 1
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 6/48
Number of signals used by logic mapping into function block: 6
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 (b)
(unused) 0 0 0 5 FB2_2 60 I/O I
(unused) 0 0 0 5 FB2_3 58 I/O I
(unused) 0 0 0 5 FB2_4 59 I/O I
(unused) 0 0 0 5 FB2_5 61 I/O I
(unused) 0 0 0 5 FB2_6 62 I/O I
(unused) 0 0 0 5 FB2_7 (b)
(unused) 0 0 0 5 FB2_8 63 I/O I
(unused) 0 0 0 5 FB2_9 64 GSR/I/O I
IDE_CS0 1 0 0 4 FB2_10 STD 1 I/O O
IDE_RST 1 0 0 4 FB2_11 STD 2 GTS/I/O O
IDE_CS1 1 0 0 4 FB2_12 STD 4 I/O O
(unused) 0 0 0 5 FB2_13 (b)
IDE_IOW 1 0 0 4 FB2_14 STD 5 GTS/I/O O
IDE_IOR 1 0 0 4 FB2_15 STD 6 I/O O
(unused) 0 0 0 5 FB2_16 (b)
(unused) 0 0 0 5 FB2_17 7 I/O
(unused) 0 0 0 5 FB2_18 (b)
Signals Used by Logic in Function Block
1: NRD 3: ADDR6 5: NCS2
2: ADDR5 4: NRST 6: NWE
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
IDE_CS0 .X...................................... 1 1
IDE_RST ...X.................................... 1 1
IDE_CS1 ..X..................................... 1 1
IDE_IOW ....XX.................................. 2 2
IDE_IOR X...X................................... 2 2
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 4/50
Number of signals used by logic mapping into function block: 4
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB3_1 (b)
(unused) 0 0 0 5 FB3_2 22 I/O I
(unused) 0 0 0 5 FB3_3 31 I/O I
BUF_DIR 1 0 0 4 FB3_4 STD 32 I/O O
(unused) 0 0 0 5 FB3_5 24 I/O I
(unused) 0 0 0 5 FB3_6 34 I/O
(unused) 0 0 0 5 FB3_7 (b)
(unused) 0 0 0 5 FB3_8 25 I/O I
(unused) 0 0 0 5 FB3_9 27 I/O I
(unused) 0 0 0 5 FB3_10 39 I/O
BUF_OE 1 0 0 4 FB3_11 STD 33 I/O O
(unused) 0 0 0 5 FB3_12 40 I/O
(unused) 0 0 0 5 FB3_13 (b)
(unused) 0 0 0 5 FB3_14 35 I/O
(unused) 0 0 0 5 FB3_15 36 I/O
(unused) 0 0 0 5 FB3_16 42 I/O
(unused) 0 0 0 5 FB3_17 38 I/O
(unused) 0 0 0 5 FB3_18 (b)
Signals Used by Logic in Function Block
1: NRD 3: NCS3 4: NCS4
2: NCS2
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
BUF_DIR X....................................... 1 1
BUF_OE .XXX.................................... 3 3
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
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