top.par

FPGA自FX2 slavefifo中读取数据

Release 6.2i Par G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

CAOLIU::  Fri Dec 15 10:35:29 2006


D:/install/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 top_map.ncd
top.ncd top.pcf 


Constraints file: top.pcf

Loading device database for application Par from file "top_map.ncd".
   "top" is an NCD, version 2.38, device xc3s400, package pq208, speed -4
Loading device for application Par from file '3s400.nph' in environment
D:/install/Xilinx.
Device speed data version:  ADVANCED 1.29 2003-12-13.


Resolved that IOB <addr_SRAM<3>> must be placed at site P203.
Resolved that IOB <addr_SRAM<4>> must be placed at site P200.
Resolved that IOB <addr_SRAM<5>> must be placed at site P199.
Resolved that IOB <led> must be placed at site P111.
Resolved that IOB <addr_SRAM<6>> must be placed at site P198.
Resolved that IOB <addr_SRAM<7>> must be placed at site P5.
Resolved that IOB <addr_SRAM<8>> must be placed at site P7.
Resolved that IOB <addr_SRAM<9>> must be placed at site P9.
Resolved that IOB <clk> must be placed at site P80.
Resolved that IOB <CE_SRAM> must be placed at site P68.
Resolved that IOB <addr_SRAM<10>> must be placed at site P10.
Resolved that IOB <addr_SRAM<11>> must be placed at site P24.
Resolved that IOB <addr_SRAM<12>> must be placed at site P26.
Resolved that IOB <addr_SRAM<13>> must be placed at site P27.
Resolved that IOB <addr_SRAM<14>> must be placed at site P28.
Resolved that IOB <addr_SRAM<15>> must be placed at site P29.
Resolved that IOB <data_SRAM<0>> must be placed at site P21.
Resolved that IOB <data_SRAM<1>> must be placed at site P20.
Resolved that IOB <empty_flag> must be placed at site P185.
Resolved that IOB <data_SRAM<2>> must be placed at site P19.
Resolved that IOB <data_SRAM<3>> must be placed at site P18.
Resolved that IOB <data_SRAM<4>> must be placed at site P16.
Resolved that IOB <data_SRAM<5>> must be placed at site P15.
Resolved that IOB <data_SRAM<6>> must be placed at site P13.
Resolved that IOB <data_SRAM<7>> must be placed at site P12.
Resolved that IOB <sloe> must be placed at site P182.
Resolved that IOB <fifoaddr<0>> must be placed at site P181.
Resolved that IOB <fifoaddr<1>> must be placed at site P180.
Resolved that IOB <LB_SRAM> must be placed at site P77.
Resolved that IOB <UB_SRAM> must be placed at site P78.
Resolved that IOB <fifodata<0>> must be placed at site P168.
Resolved that IOB <fifodata<1>> must be placed at site P169.
Resolved that IOB <fifodata<2>> must be placed at site P171.
Resolved that IOB <reset> must be placed at site P87.
Resolved that IOB <fifodata<3>> must be placed at site P172.
Resolved that IOB <fifodata<4>> must be placed at site P196.
Resolved that IOB <fifodata<5>> must be placed at site P194.
Resolved that IOB <OE_SRAM> must be placed at site P39.
Resolved that IOB <fifodata<6>> must be placed at site P191.
Resolved that IOB <fifodata<7>> must be placed at site P190.
Resolved that IOB <WE_SRAM> must be placed at site P11.
Resolved that IOB <slrd> must be placed at site P165.
Resolved that IOB <addr_SRAM<0>> must be placed at site P43.
Resolved that IOB <addr_SRAM<1>> must be placed at site P42.
Resolved that IOB <addr_SRAM<2>> must be placed at site P40.


Device utilization summary:

   Number of External IOBs            45 out of 141    31%
      Number of LOCed External IOBs   45 out of 45    100%

   Number of Slices                   56 out of 3584    1%

   Number of BUFGMUXs                  1 out of 8      12%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989841) REAL time: 0 secs 

.
Phase 3.8
.
Phase 3.8 (Checksum:998eb3) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.18
Phase 5.18 (Checksum:2faf07b) REAL time: 0 secs 

Writing design to file top.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 435 unrouted;       REAL time: 2 secs 

Phase 2: 385 unrouted;       REAL time: 2 secs 

Phase 3: 159 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 

Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 1 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|         clk_BUFGP       |  BUFGMUX1| No   |    6 |  0.001     |  0.585      |
+-------------------------+----------+------+------+------------+-------------+
|         count<10>       |   Local  |      |   36 |  0.205     |  1.861      |
+-------------------------+----------+------+------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 158


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.040
   The MAXIMUM PIN DELAY IS:                               3.804
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.709

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         251         160          16           8           0           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  68 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file top.ncd.


PAR done.