top(读flag另为一个状态).vhdl

FPGA自FX2 slavefifo中读取数据

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top is
  port( 
  		clk  : 	in std_logic;
		slrd: buffer std_logic;	 -- read strobe
	     sloe: out std_logic;	      -- output enable
	     fifoaddr: out std_logic_vector(1 downto 0);
	     fifodata: in std_logic_vector(7 downto 0);   -- out data
          empty_flag : in std_logic;	  -- FLAGC

		reset:	in std_logic;
	  	addr_SRAM:out std_logic_vector(15 downto 0);
	   	data_SRAM:out std_logic_vector(7 downto 0);
	   	WE_SRAM:	out std_logic;
    	   	OE_SRAM:	out std_logic;
	   	CE_SRAM:	out std_logic;
	   	LB_SRAM:	out std_logic;
	   	UB_SRAM:	out std_logic;
		led:		out std_logic
	   ) ;       
end top;


architecture Behavioral of top is

signal count : 	std_logic_vector(10 downto 0);
signal clk_SRAM: 		std_logic;

begin

process(clk)
begin
    	if clk'event and clk='1' then
		 count<=count+'1'; 
	end if;
end process;

clk_SRAM<=count(10);


process(clk_SRAM, reset)

variable temp_addr_SRAM: std_logic_vector(15 downto 0);	-- 地址变量
variable data_in:		std_logic_vector(7 downto 0);	    	-- 数据变量
variable state:	integer range 0 to 6;				-- 状态变量
variable is_end:	std_logic;				    		-- 写数据结束标志
variable flag:		std_logic;
begin

if clk_SRAM'event and clk_SRAM='1' then

	if reset='1' then	-- 复位
		is_end:='0';	-- 写结束标芯初始化

		state:=0;		-- 状态变量初始化
	else
		if is_end='0' then	-- 写数据没有结束
			case state is
				when 0 =>
					fifoaddr<="00";  -- 地址应该为EP2
					OE_SRAM<='0';	-- 输出使能
					CE_SRAM<='0';	-- 芯片使能
					LB_SRAM<='1';	-- 低位禁能
					UB_SRAM<='1';  -- 高位禁能
					WE_SRAM<='1';	-- 写禁能
					led<='0';		-- LED 亮
					temp_addr_SRAM:=(others=>'0');	-- 地址初始化
					slrd<='1';	-- FX2 读禁能
					sloe<='1';	-- FX2 输出禁能
					state:=1;
				when 1 =>
					flag:=empty_flag; --and start;
					state:=2;
				when 2 =>
					if flag='1' then	 	 -- check empty flag
						sloe<='0';		 -- assert SLOE
						slrd<='0';     	 -- assert SLWR
						state:=3;			 -- 转到状态1
		     		else 
						state:=1;			 -- 若FIFO空，仍为状态0，等待
	     			end if;  	
				when 3 =>
					data_in:=fifodata;	 -- 读FIFO数据
					state:=4;
				when 4 => 
					sloe<='1';			 -- 输出禁能
					slrd<='1';			 -- 读禁能，地址加一
					addr_SRAM<=temp_addr_SRAM;	-- 送地址
					data_SRAM<= data_in;  		-- 送数据
					state:=5;				     -- 转到状态3
				when 5 => 
					WE_SRAM<='0';	  			-- 写使能
					LB_SRAM<='0';				-- 低位使能	 		
					state:=6;		   			-- 转到状态4
				when 6 => 
					WE_SRAM<='1';					-- 写禁能
					LB_SRAM<='1';	 				-- 低位禁能
					temp_addr_SRAM:=temp_addr_SRAM+1; 	-- 地址变量加1
					state:=1;						-- 转到状态0
					if temp_addr_SRAM="0001000000000000" then	-- 已写满
					  is_end:='1';					-- 写结束标志置位
					  led<='1';					-- LED 暗
					end if;

			end case;

		end if;

	end if;
end if;

end process;
				
end 	 Behavioral;