adsp-bf535_asm.ldf

bf535 rtc example code.

ARCHITECTURE(ADSP-BF535)
SEARCH_DIR( $ADI_DSP/Blackfin/lib )

$OBJECTS = $COMMAND_LINE_OBJECTS;
//$LIBRARIES = librt.dlb;
$LIBRARIES = $COMMAND_LINE_OBJECTS;

/*
** EZ-KIT Lite Evaluation Board Memory Map.
** 
** The known memory spaces are as follows:
** 
** 0xFFE00000 - 0xFFFFFFFF		Core MMR registers (2MB)
** 0xFFC00000 - 0xFFDFFFFF		System MMR registers (2MB)
** 0xFFB04000 - 0xFFBFFFFF		Reserved
** 0xFFB00000 - 0xFFB00FFF		Scratch SRAM (4K)
** 0xFFA04000 - 0xFFAFFFFF		Reserved
** 0xFFA00000 - 0xFFA03FFF		Code SRAM (16K)
** 0xFF904000 - 0xFF9FFFFF		Reserved
** 0xFF900000 - 0xFF903FFF		Data Bank B SRAM (16K)
** 0xFF804000 - 0xFF8FFFFF		Reserved
** 0xFF800000 - 0xFF803FFF		Data Bank A SRAM (16K)
** 0xF0040000 - 0xFF7FFFFF		Reserved RAM
** 0xF0000000 - 0xF003FFFF		L2 SRAM (256K)
** 0xEF000400 - 0xEFFFFFFF		Reserved ROM
** 0xEF000000 - 0xEF0003FF		Boot ROM (1K)
** 0x00000000 - 0xEEFFFFFF		unpopulated
*/

MEMORY
{
		
	/** Level 1 Memory **/
	SCRATCH	{ TYPE(RAM) START(0xFFB00000) END(0xFFB00FFF) WIDTH(8) }
	CODE		{ TYPE(RAM) START(0xFFA00000) END(0xFFA03FFF) WIDTH(8) }

	/** Data Bank B SRAM **/
	DATA_B_0	{ TYPE(RAM) START(0xFF900000) END(0xFF900FFF) WIDTH(8) }	// super-bank B, mini-bank 0
	DATA_B_1	{ TYPE(RAM) START(0xFF901000) END(0xFF901FFF) WIDTH(8) }	// super-bank B, mini-bank 1
	DATA_B_2	{ TYPE(RAM) START(0xFF902000) END(0xFF902FFF) WIDTH(8) }	// super-bank B, mini-bank 2
	DATA_B_3	{ TYPE(RAM) START(0xFF903000) END(0xFF903FFF) WIDTH(8) }	// super-bank B, mini-bank 3
	
	/** Data Bank A SRAM **/
	DATA_A_0	{ TYPE(RAM) START(0xFF800000) END(0xFF800FFF) WIDTH(8) }	// super-bank A, mini-bank 0
	DATA_A_1	{ TYPE(RAM) START(0xFF801000) END(0xFF801FFF) WIDTH(8) }	// super-bank A, mini-bank 1
	DATA_A_2	{ TYPE(RAM) START(0xFF802000) END(0xFF802FFF) WIDTH(8) }	// super-bank A, mini-bank 2
	DATA_A_3	{ TYPE(RAM) START(0xFF803000) END(0xFF803FFF) WIDTH(8) }	// super-bank A, mini-bank 3
	
	/** Level 2 Memory **/
	L2_BANK0	{ TYPE(RAM) START(0xF0000000) END(0xF0003FFF) WIDTH(8) }
	
}

PROCESSOR p0
{
    OUTPUT( $COMMAND_LINE_OUTPUT_FILE )

    SECTIONS
    {
        code
        {
        	INPUT_SECTION_ALIGN(2)	// align all code sections on 2 byte boundary
        	INPUT_SECTIONS( $OBJECTS(program) $LIBRARIES(program) )
		}>CODE

        data_a
        {
        	INPUT_SECTION_ALIGN(1)	// the data sections should be aligned in the code
        	INPUT_SECTIONS( $OBJECTS(data_a) $LIBRARIES(data_a) )
		}>DATA_A_0        

        
		data_b
        {
        	INPUT_SECTION_ALIGN(1)	// the data sections should be aligned in the code
        	INPUT_SECTIONS( $OBJECTS(data_b) $LIBRARIES(data_b) )
		}>DATA_B_1 
		
		l2_bank0
		{
		    INPUT_SECTION_ALIGN(1)	// the data sections should be aligned in the code
        	INPUT_SECTIONS( $OBJECTS(l2_bank0) $LIBRARIES(l2_bank0) )
		}>L2_BANK0
		
		
    }
}