📄 adi_audioezextender.c
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//=================================================================================
// Audio EZ-Extender mode specific definition
#define SPDIF_TX_FREQ_SPDIF_RX_CLK 1
#define SPDIF_TX_FREQ_192K 2
#define SPDIF_TX_FREQ_144K 21
#define SPDIF_TX_FREQ_96K 3
#define SPDIF_TX_FREQ_48K 4
#define SPDIF_RX_DEST_BOTH 5
#define SPDIF_RX_DEST_SECONDARY 6
#define SPDIF_RX_DEST_PRIMARY 7
#define SPDIF_RX_DEST_DISABLED 8
#define SPDIF_TX_SRC_DISABLED 9
#define SPDIF_TX_SRC_PRIMARY 10
#define SPDIF_TX_SRC_SECONDARY 11
#define SPDIF_TX_CLK_SELECT_SPDIF_RX_CLK 12
#define SPDIF_TX_CLK_SELECT_INTCLK1 13
#define SCLK3_SRC_SPDIF_RX_CLK_MODE 14
#define SCLK3_SRC_PLL2_CLK_MODE 15
#define ANALOG_INPUT_MODE_AUX 16
#define ANALOG_INPUT_MODE_TDM 17
#define ANALOG_OUTPUT_MODE_AUX 16
#define ANALOG_OUTPUT_MODE_TDM 17
//=================================================================================
// Audio EZ-Extender mode specific data
#if (ADAV801_SUPPORT)
// ADAV801 driver specific configuration command pair
volatile ADI_DEV_CMD_VALUE_PAIR ADAV801_Config [] =
{
{ ADI_ADAV801_CMD_SET_SPI_SLAVE_SELECT, (void *)1 }, // ADAV801 slave select for BF537
{ ADI_ADAV801_CMD_SET_REG_00, (void*)0 },
{ ADI_ADAV801_CMD_SET_REG_03, (void*)0 },
{ ADI_ADAV801_CMD_SET_REG_04, (void*)0 },
{ ADI_ADAV801_CMD_SET_REG_05, (void*)0 },
{ ADI_ADAV801_CMD_SET_REG_06, (void*)0 },
{ ADI_ADAV801_CMD_SET_REG_07, (void*)0 },
{ ADI_ADAV801_CMD_SET_REG_09, (void*)0 },
{ ADI_ADAV801_CMD_SET_REG_0A, (void*)0 },
{ ADI_ADAV801_CMD_SET_REG_0B, (void*)0 },
{ ADI_ADAV801_CMD_SET_REG_0C, (void*)0 },
{ ADI_ADAV801_CMD_SET_REG_1E, (void*)0 },
{ ADI_ADAV801_CMD_SET_REG_62, (void*)0 },
{ ADI_ADAV801_CMD_SET_REG_63, (void*)0 },
{ ADI_ADAV801_CMD_SET_REG_64, (void*)0 },
{ ADI_ADAV801_CMD_SET_REG_65, (void*)0 },
{ ADI_ADAV801_CMD_SET_REG_6E, (void*)0 },
{ ADI_ADAV801_CMD_SET_REG_6F, (void*)0 },
{ ADI_ADAV801_CMD_SET_REG_74, (void*)0 },
{ ADI_ADAV801_CMD_SET_REG_75, (void*)0 },
{ ADI_ADAV801_CMD_SET_REG_76, (void*)0 },
{ ADI_ADAV801_CMD_SET_REG_77, (void*)0 },
{ ADI_ADAV801_CMD_SET_REG_78, (void*)0 },
{ ADI_ADAV801_CMD_SET_REG_7A, (void*)0 },
{ ADI_DEV_CMD_END, NULL },
};
#endif
// AD1938 A codec specific configuration command pair
volatile ADI_DEV_CMD_VALUE_PAIR AD1938_A_Config [] =
{
{ ADI_AD1938_CMD_SET_SPI_SLAVE_SELECT, (void *)5 }, // AD1938-A slave select for BF537
{ ADI_AD1938_CMD_SET_PLL_CLOCK_CONTROL_0, (void*)0 },
{ ADI_AD1938_CMD_SET_PLL_CLOCK_CONTROL_1, (void*)0 },
{ ADI_AD1938_CMD_SET_DAC_CONTROL_0, (void*)0 },
{ ADI_AD1938_CMD_SET_DAC_CONTROL_1, (void*)0 },
{ ADI_AD1938_CMD_SET_DAC_CONTROL_2, (void*)0 },
{ ADI_AD1938_CMD_SET_ADC_CONTROL_0, (void*)0 },
{ ADI_AD1938_CMD_SET_ADC_CONTROL_1, (void*)0 },
{ ADI_AD1938_CMD_SET_ADC_CONTROL_2, (void*)0 },
{ ADI_AD1938_CMD_SET_DAC_CHANNEL_MUTES, (void*)0 },
{ ADI_AD1938_CMD_SET_DAC_1LVOLUME_CONTROL, (void*)0 },
{ ADI_AD1938_CMD_SET_DAC_1RVOLUME_CONTROL, (void*)0 },
{ ADI_AD1938_CMD_SET_DAC_2LVOLUME_CONTROL, (void*)0 },
{ ADI_AD1938_CMD_SET_DAC_2RVOLUME_CONTROL, (void*)0 },
{ ADI_AD1938_CMD_SET_DAC_3LVOLUME_CONTROL, (void*)0 },
{ ADI_AD1938_CMD_SET_DAC_3RVOLUME_CONTROL, (void*)0 },
{ ADI_AD1938_CMD_SET_DAC_4LVOLUME_CONTROL, (void*)0 },
{ ADI_AD1938_CMD_SET_DAC_4RVOLUME_CONTROL, (void*)0 },
{ ADI_AD1938_CMD_SET_PLL_CLOCK_CONTROL_0, (void*)0 },
{ ADI_AD1938_CMD_SET_PLL_CLOCK_CONTROL_0, (void*)0 },
{ ADI_DEV_CMD_END, NULL },
};
// AD1938 B codec specific configuration command pair
volatile ADI_DEV_CMD_VALUE_PAIR AD1938_B_Config [] =
{
{ ADI_AD1938_CMD_SET_SPI_SLAVE_SELECT, (void *)6 }, // AD1938-B slave select for BF537
{ ADI_AD1938_CMD_SET_PLL_CLOCK_CONTROL_0, (void*)0 },
{ ADI_AD1938_CMD_SET_PLL_CLOCK_CONTROL_1, (void*)0 },
{ ADI_AD1938_CMD_SET_DAC_CONTROL_0, (void*)0 },
{ ADI_AD1938_CMD_SET_DAC_CONTROL_1, (void*)0 },
{ ADI_AD1938_CMD_SET_DAC_CONTROL_2, (void*)0 },
{ ADI_AD1938_CMD_SET_ADC_CONTROL_0, (void*)0 },
{ ADI_AD1938_CMD_SET_ADC_CONTROL_1, (void*)0 },
{ ADI_AD1938_CMD_SET_ADC_CONTROL_2, (void*)0 },
{ ADI_AD1938_CMD_SET_DAC_CHANNEL_MUTES, (void*)0 },
{ ADI_AD1938_CMD_SET_DAC_1LVOLUME_CONTROL, (void*)0 },
{ ADI_AD1938_CMD_SET_DAC_1RVOLUME_CONTROL, (void*)0 },
{ ADI_AD1938_CMD_SET_DAC_2LVOLUME_CONTROL, (void*)0 },
{ ADI_AD1938_CMD_SET_DAC_2RVOLUME_CONTROL, (void*)0 },
{ ADI_AD1938_CMD_SET_DAC_3LVOLUME_CONTROL, (void*)0 },
{ ADI_AD1938_CMD_SET_DAC_3RVOLUME_CONTROL, (void*)0 },
{ ADI_AD1938_CMD_SET_DAC_4LVOLUME_CONTROL, (void*)0 },
{ ADI_AD1938_CMD_SET_DAC_4RVOLUME_CONTROL, (void*)0 },
{ ADI_AD1938_CMD_SET_PLL_CLOCK_CONTROL_0, (void*)0 },
{ ADI_AD1938_CMD_SET_PLL_CLOCK_CONTROL_0, (void*)0 },
{ ADI_DEV_CMD_END, NULL },
};
// digital mode index mapping table for configuration
int DigitalConstant[16][4] =
{
{ 0, 0, 0, 0 },
{ SPDIF_TX_FREQ_192K, SPDIF_TX_SRC_PRIMARY, SPDIF_RX_DEST_PRIMARY, SCLK3_SRC_SPDIF_RX_CLK_MODE },
{ SPDIF_TX_FREQ_48K, SPDIF_TX_SRC_PRIMARY, SPDIF_RX_DEST_PRIMARY, SCLK3_SRC_SPDIF_RX_CLK_MODE },
{ SPDIF_TX_FREQ_96K, SPDIF_TX_SRC_PRIMARY, SPDIF_RX_DEST_PRIMARY, SCLK3_SRC_SPDIF_RX_CLK_MODE },
{ SPDIF_TX_FREQ_SPDIF_RX_CLK, SPDIF_TX_SRC_PRIMARY, SPDIF_RX_DEST_PRIMARY, SCLK3_SRC_SPDIF_RX_CLK_MODE },
{ SPDIF_TX_FREQ_192K, SPDIF_TX_SRC_PRIMARY, SPDIF_RX_DEST_PRIMARY, SCLK3_SRC_PLL2_CLK_MODE },
{ SPDIF_TX_FREQ_48K, SPDIF_TX_SRC_PRIMARY, SPDIF_RX_DEST_PRIMARY, SCLK3_SRC_PLL2_CLK_MODE },
{ SPDIF_TX_FREQ_96K, SPDIF_TX_SRC_PRIMARY, SPDIF_RX_DEST_PRIMARY, SCLK3_SRC_PLL2_CLK_MODE },
{ SPDIF_TX_FREQ_SPDIF_RX_CLK, SPDIF_TX_SRC_PRIMARY, SPDIF_RX_DEST_PRIMARY, SCLK3_SRC_PLL2_CLK_MODE },
{ SPDIF_TX_FREQ_48K, SPDIF_TX_SRC_SECONDARY, SPDIF_RX_DEST_PRIMARY, SCLK3_SRC_PLL2_CLK_MODE },
{ SPDIF_TX_FREQ_192K, SPDIF_TX_SRC_PRIMARY, SPDIF_RX_DEST_SECONDARY, SCLK3_SRC_SPDIF_RX_CLK_MODE },
{ SPDIF_TX_FREQ_48K, SPDIF_TX_SRC_PRIMARY, SPDIF_RX_DEST_SECONDARY, SCLK3_SRC_SPDIF_RX_CLK_MODE },
{ SPDIF_TX_FREQ_96K, SPDIF_TX_SRC_PRIMARY, SPDIF_RX_DEST_SECONDARY, SCLK3_SRC_SPDIF_RX_CLK_MODE },
{ SPDIF_TX_FREQ_SPDIF_RX_CLK, SPDIF_TX_SRC_PRIMARY, SPDIF_RX_DEST_SECONDARY, SCLK3_SRC_SPDIF_RX_CLK_MODE },
{ SPDIF_TX_FREQ_SPDIF_RX_CLK, SPDIF_TX_SRC_SECONDARY, SPDIF_RX_DEST_SECONDARY, SCLK3_SRC_SPDIF_RX_CLK_MODE },
{ SPDIF_TX_FREQ_SPDIF_RX_CLK, SPDIF_TX_SRC_SECONDARY, SPDIF_RX_DEST_PRIMARY, SCLK3_SRC_SPDIF_RX_CLK_MODE },
};
// local variables for configuring Audio EZ-Extender
static int cSPDIF_TX_FREQ;
static int cSPDIF_TX_SRC;
static int cSPDIF_RX_DEST;
static int cSCLK3_SRC_MODE;
static int cSPDIF_TX_CLK_SELECT;
static int cFS2_FS_SEL;
static int cFS2_FS_RATIO;
static int cFS2_MUL;
static int cFS3_FS_RATIO;
static int cPLL2_DIV;
static int cINTCLK1_SRC;
static int cINTCLK1_DIV;
static int cPRI_RX_CLK_SRC;
static int cSEC_RX_CLK_SRC;
static int cSPDIF_TX_DAT_SRC;
static int cSPDIF_TX_CLK_SRC;
static int cPRI_TX_CLK_SRC;
static int cPRI_TX_DAT_SRC;
static int cSEC_TX_CLK_SRC;
static int cSEC_TX_DAT_SRC;
static int cSCLK3_SRC;
static int cINPUT_MUL;
static int cFS1_FS_SEL;
static int cFS1_FS_RATIO;
static int cFS1_MUL;
static int cPLL1_DIV;
static int cINTCLK2_SRC;
static int cINTCLK2_DIV;
static int cANALOG_SR;
static int cTDM_SLOTS;
static int cANALOG_INPUT_MODE;
static int cANALOG_OUTPUT_MODE;
static int cDAC_FMT;
static int cADC_FMT;
static int cDAC_SAMPLE_RATE;
static int cADC_SAMPLE_RATE;
static int cDAC_CHANNELS;
static int cADC_CHANNELS;
// DMA channel layout of Audio EZ-Extender
static int cADC_L1;
static int cADC_R1;
static int cADC_L2;
static int cADC_R2;
static int cADC_L3;
static int cADC_R3;
static int cADC_L4;
static int cADC_R4;
static int cSPDIF_RX_L;
static int cSPDIF_RX_R;
static int cDAC_L1;
static int cDAC_R1;
static int cDAC_L2;
static int cDAC_R2;
static int cDAC_L3;
static int cDAC_R3;
static int cDAC_L4;
static int cDAC_R4;
static int cDAC_L5;
static int cDAC_R5;
static int cDAC_L6;
static int cDAC_R6;
static int cDAC_L7;
static int cDAC_R7;
static int cDAC_L8;
static int cDAC_R8;
static int cSPDIF_TX_L;
static int cSPDIF_TX_R;
/**********************************************************************************
Driver specific definitions / prototype / data
**********************************************************************************/
// type definition of physical driver instance
typedef struct
{
ADI_DEV_MANAGER_HANDLE ManagerHandle; // Manager Handle
ADI_DEV_DEVICE_HANDLE DMHandle; // Handle of Device Manager instance
ADI_DMA_MANAGER_HANDLE DMAHandle; // handle to the DMA manager
ADI_DCB_HANDLE DCBHandle; // callback handle
u32 InUseFlag; // flag to indicate whether an instance is in use or not
ADI_DCB_CALLBACK_FN DMCallback; // the callback function supplied by the Device Manager
ADI_DEV_PDD_HANDLE AD1938Handle; // handle for AD1938 A&B device
ADI_DEV_PDD_HANDLE ADAV801Handle; // handle for ADAV801 device
u32 AnalogMode; // analog mode selection
u32 DigitalMode; // digital mode selection
u32 SportSelect; // select SPORT0/1 jumper setting on the board
// select which device the read/write/control message is redirected to
AUDIOEZEXTENDER_CODEC_SELECTION SelectedDevice;
}
ADI_AUDIOEZEXTENDER;
// The initial values for the device instance
static ADI_AUDIOEZEXTENDER Device[] =
{
{
NULL,
NULL,
NULL,
NULL,
false,
NULL,
NULL, // AD1938 device handle
NULL, // ADAV801 device handle
0, // analog mode index
6, // digital mode index
0, // 0: OFF SPORT1 selected for SPORT A
ADI_AD1938, // default device
},
};
// forward declaration for callback function
static void AudioEZExtenderCallbackFunction(void* DeviceHandle, u32 Event, void* pArg);
/*********************************************************************
*
* Function: setAudioMode
*
* Description: Configuration command for each device is determined here
* based on analog and digital mode index number.
* It calls driver control functions to configure each.
*
*********************************************************************/
static void setAudioMode(ADI_AUDIOEZEXTENDER *pAUDIOEZEXTENDER)
{
u32 Result = ADI_DEV_RESULT_SUCCESS;
// get the local parameters from the digital mode index
cSPDIF_TX_FREQ = DigitalConstant[pAUDIOEZEXTENDER->DigitalMode][0];
cSPDIF_TX_SRC = DigitalConstant[pAUDIOEZEXTENDER->DigitalMode][1];
cSPDIF_RX_DEST = DigitalConstant[pAUDIOEZEXTENDER->DigitalMode][2];
cSCLK3_SRC_MODE = DigitalConstant[pAUDIOEZEXTENDER->DigitalMode][3];
switch (cSPDIF_TX_FREQ)
{
case SPDIF_TX_FREQ_48K:
cSPDIF_TX_CLK_SELECT = SPDIF_TX_CLK_SELECT_INTCLK1;
//PLL2/SCLK2/SCLK3 Setup
cFS2_FS_SEL = FS2_FS_SEL_48K;
cFS2_FS_RATIO = FS2_FS_RATIO_256FS;
cFS2_MUL = FS2_MUL_1;
cFS3_FS_RATIO = FS3_FS_RATIO_512FS;
cPLL2_DIV = PLL2_FS2_DIV_1;
//INTCLK1 Setup
cINTCLK1_SRC = INTCLK1_SRC_PLLINT2;
cINTCLK1_DIV = INTCLK1_DIV_1;
break;
case SPDIF_TX_FREQ_96K:
cSPDIF_TX_CLK_SELECT = SPDIF_TX_CLK_SELECT_INTCLK1;
//PLL2/SCLK2/SCLK3 Setup
cFS2_FS_SEL = FS2_FS_SEL_48K;
cFS2_FS_RATIO = FS2_FS_RATIO_256FS;
cFS2_MUL = FS2_MUL_1;
cFS3_FS_RATIO = FS3_FS_RATIO_512FS;
cPLL2_DIV = PLL2_FS3_DIV_1;
//INTCLK1 Setup
cINTCLK1_SRC = INTCLK1_SRC_PLLINT2;
cINTCLK1_DIV = INTCLK1_DIV_1;
break;
case SPDIF_TX_FREQ_192K:
//IMPORTANT NOTE: to use this mode you need to change the jumper JP2 to use SYSCLK1
cSPDIF_TX_CLK_SELECT = SPDIF_TX_CLK_SELECT_INTCLK1;
//PLL2/SCLK2/SCLK3 Setup
cFS2_FS_SEL = FS2_FS_SEL_48K;
cFS2_FS_RATIO = FS2_FS_RATIO_256FS;
cFS2_MUL = FS2_MUL_2;
cFS3_FS_RATIO = FS3_FS_RATIO_512FS;
cPLL2_DIV = PLL2_FS3_DIV_1;
//INTCLK1 Setup
cINTCLK1_SRC = INTCLK1_SRC_PLLINT2;
cINTCLK1_DIV = INTCLK1_DIV_1;
break;
case SPDIF_TX_FREQ_SPDIF_RX_CLK:
cSPDIF_TX_CLK_SELECT = SPDIF_TX_CLK_SELECT_SPDIF_RX_CLK;
//PLL2/SCLK2/SCLK3 Setup
cFS2_FS_SEL = FS2_FS_SEL_48K;
cFS2_FS_RATIO = FS2_FS_RATIO_256FS;
cFS2_MUL = FS2_MUL_1;
cFS3_FS_RATIO = FS3_FS_RATIO_512FS;
cPLL2_DIV = PLL2_FS2_DIV_1;
//INTCLK1 Setup
cINTCLK1_SRC = INTCLK1_SRC_PLLINT2;
cINTCLK1_DIV = INTCLK1_DIV_1;
break;
}
switch (cSPDIF_TX_SRC)
{
case SPDIF_TX_SRC_DISABLED:
if (cSPDIF_TX_CLK_SELECT == SPDIF_TX_CLK_SELECT_INTCLK1)
{
cPRI_RX_CLK_SRC = PRI_RX_CLK_SRC_SLAVE;
cSEC_RX_CLK_SRC = SEC_RX_CLK_SRC_SPDIF_RX_CLK;
cSPDIF_TX_DAT_SRC = SPDIF_TX_DAT_SRC_PRI_RX;
cSPDIF_TX_CLK_SRC = SPDIF_TX_CLK_SRC_INTCLK1;
}
else if (cSPDIF_TX_CLK_SELECT == SPDIF_TX_CLK_SELECT_SPDIF_RX_CLK)
{
cPRI_RX_CLK_SRC = PRI_RX_CLK_SRC_SLAVE;
cSEC_RX_CLK_SRC = SEC_RX_CLK_SRC_SPDIF_RX_CLK;
cSPDIF_TX_DAT_SRC = SPDIF_TX_DAT_SRC_PRI_RX;
cSPDIF_TX_CLK_SRC = SPDIF_TX_CLK_SRC_SPDIF_RX_CLK;
}
break;
case SPDIF_TX_SRC_PRIMARY:
if (cSPDIF_TX_CLK_SELECT == SPDIF_TX_CLK_SELECT_INTCLK1)
{
cPRI_RX_CLK_SRC = PRI_RX_CLK_SRC_INTCLK1;
cSEC_RX_CLK_SRC = SEC_RX_CLK_SRC_SPDIF_RX_CLK;
cSPDIF_TX_DAT_SRC = SPDIF_TX_DAT_SRC_PRI_RX;
cSPDIF_TX_CLK_SRC = SPDIF_TX_CLK_SRC_INTCLK1;
}
else if (cSPDIF_TX_CLK_SELECT == SPDIF_TX_CLK_SELECT_SPDIF_RX_CLK)
{
cPRI_RX_CLK_SRC = PRI_RX_CLK_SRC_SPDIF_RX_CLK;
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