adi_audioezextender.c

audio talktrough code. platform bf533 + audio card.

/*********************************************************************************

Copyright(c) 2005 Analog Devices, Inc. All Rights Reserved.

This software is proprietary and confidential.  By using this software you agree
to the terms of the associated Analog Devices License Agreement.

*********************************************************************************/
/*************************************************************************************

Description:        This is the virtual driver source code for Audio EZ-Extender. 
                    It is layered on top of the AD1938 and ADAV801 device drivers, 
                    which configure various audio modes.
			        Currently the audio mode is fixed for BF537 and the ADAV801 driver 
			        is not available.  Only SPORT1 is used.
                    The driver opens the SPI and SPORT devices on the ADSP-BF537 and uses
                    them to configure the AD1938 codec A and B.
                    And then transfers audio data to/from the DAC and ADC over SPORT1 in TDM mode.
                        
Hardware:           ADSP-BF537 EZ-KIT Board	Rev. 1.1
                    Audio EZ-Extender Card Rev. 1.0/1.1

Hardware Setup:     Connect the Audio EZ-Extender Card to the EZ-KIT 
                    Settings of the switches on the Audio EZ-Extender Card:
                    SPORT1 MODE:
                        			JP1-> 1-2 (BF537_SEL)
									JP1-> 5-6 (SPORT1_EN)
									JP2-> 5-6 (ADAV801_SYSCLK3)

                    Settings of the switches on the EZ-Kit:
                    Switch all SW to default settings, then
                        SW5 - all OFF
                        SW7 - 6 OFF
                            - 8 OFF

*********************************************************************************/


/*********************************************************************

Include files

*********************************************************************/

#include <services\services.h>          // system service include file
#include <drivers\adi_dev.h>                    // device manager include file
#include <drivers\adi_spi.h>            // spi driver include file
#include <drivers\adi_sport.h>          // sport driver include file
#include <drivers\codec\adi_AD1938.h>   // AD1938 driver
#if (ADAV801_SUPPORT)
#include "adi_ADAV801.h"                // ADAV801 driver  *not included
#endif
#include "adi_AudioEZExtender.h"

/*********************************************************************

Enumerations and definitions

*********************************************************************/
// number of Audio EZ-Extender devices in the system
#define ADI_AUDIOEZEXTENDER_NUM_DEVICES	(sizeof(Device)/sizeof(ADI_AUDIOEZEXTENDER))


/**********************************************************************************

  Audio EZ-Extender specific definitions / data

**********************************************************************************/

#define b0_1	0x01
#define b1_1	0x02
#define b2_1	0x04
#define b3_1	0x08
#define b4_1	0x10
#define b5_1	0x20
#define b6_1	0x40
#define b7_1	0x80

#define b0_0	0x00
#define b1_0	0x00
#define b2_0	0x00
#define b3_0	0x00
#define b4_0	0x00
#define b5_0	0x00
#define b6_0	0x00
#define b7_0	0x00

//=================================================================================
// AD1938 CODEC

//PLL_CLK_CONTROL_0
#define DIS_ADC_DAC			(b7_0)
#define ENA_ADC_DAC			(b7_1)

#define PLL_IN_MCLK			(b6_0 | b5_0)
#define PLL_IN_DLRCLK		(b6_0 | b5_1)
#define PLL_IN_ALRCLK		(b6_1 | b5_0)

#define MCLK_OUT_XTAL		(b4_0 | b3_0)
#define MCLK_OUT_256FS		(b4_0 | b3_1)
#define MCLK_OUT_512FS		(b4_1 | b3_0)
#define MCLK_OUT_OFF		(b4_1 | b3_1)

#define INPUT256			(b2_0 | b1_0)
#define INPUT384			(b2_0 | b1_1)
#define INPUT512			(b2_1 | b1_0)
#define INPUT768			(b2_1 | b1_1)

#define PLL_PWR_UP			(b0_0)
#define PLL_PWR_DWN			(b0_1)


//PLL_CLK_CONTROL_1
#define DIS_VREF			(b2_0)
#define ENA_VREF			(b2_1)

#define ADC_CLK_PLL			(b1_0)
#define ADC_CLK_MCLK		(b1_1)

#define DAC_CLK_PLL			(b0_0)
#define DAC_CLK_MCLK		(b0_1)


//DAC_CONTROL_0
#define DAC_FMT_I2S			(b7_0 | b6_0)
#define DAC_FMT_TDM			(b7_0 | b6_1)
#define DAC_FMT_AUX			(b7_1 | b6_0)
#define DAC_FMT_DUALTDM		(b7_1 | b6_1)


#define DAC_BLK_DLY_1		(b5_0 | b4_0 | b3_0)
#define DAC_BLK_DLY_0		(b5_0 | b4_0 | b3_1)
#define DAC_BLK_DLY_8		(b5_0 | b4_1 | b3_0)
#define DAC_BLK_DLY_12		(b5_0 | b4_1 | b3_1)
#define DAC_BLK_DLY_16		(b5_1 | b4_0 | b3_0)

#define DAC_SR_48K			(b2_0 | b1_0)
#define DAC_SR_96K			(b2_0 | b1_1)
#define DAC_SR_192K			(b2_1 | b1_0)

#define DAC_PWR_UP			(b0_0)
#define DAC_PWR_DWN			(b0_1)


//DAC_CONTROL_1
#define DAC_BCLK_POL_NORM		(b7_0)
#define DAC_BCLK_POL_INV		(b7_1)

#define DAC_BCLK_SRC_PIN		(b6_0)
#define DAC_BCLK_SRC_INTERNAL	(b6_1)

#define DAC_BCLK_SLAVE			(b5_0)
#define DAC_BCLK_MASTER			(b5_1)

#define DAC_LRCLK_SLAVE			(b4_0)
#define DAC_LRCLK_MASTER		(b4_1)

#define DAC_LRCLK_POL_NORM		(b3_0)
#define DAC_LRCLK_POL_INV		(b3_1)

#define DAC_CHANNELS_2			(b2_0 | b1_0)
#define DAC_CHANNELS_4			(b2_0 | b1_1)
#define DAC_CHANNELS_8			(b2_1 | b1_0)
#define DAC_CHANNELS_16			(b2_1 | b1_1)

#define DAC_LTCH_MID			(b0_0)
#define DAC_LTCH_END			(b0_1)


//DAC_CONTROL_2
#define DAC_OUT_POL_NORM	(b5_0)
#define DAC_OUT_POL_INV		(b5_1)

#define DAC_WIDTH_24		(b4_0 | b3_0)
#define DAC_WIDTH_20		(b4_0 | b3_1)
#define DAC_WIDTH_16		(b4_1 | b3_1)

#define DAC_DEEMPH_FLAT		(b2_0 | b1_0)
#define DAC_DEEMPH_48K		(b2_0 | b1_1)
#define DAC_DEEMPH_44_1K	(b2_1 | b1_0)
#define DAC_DEEMPH_32K		(b2_1 | b1_1)

#define DAC_UNMUTE			(b0_0)
#define DAC_MUTE			(b0_1)


//ADC_CONTROL_0
#define ADC_SR_48K			(b7_0 | b6_0)
#define ADC_SR_96K			(b7_0 | b6_1)
#define ADC_SR_192K			(b7_1 | b6_0)

#define ADC_R2_UNMUTE		(b5_0)
#define ADC_R2_MUTE			(b5_1)

#define ADC_L2_UNMUTE		(b4_0)
#define ADC_L2_MUTE			(b4_1)

#define ADC_R1_UNMUTE		(b3_0)
#define ADC_R1_MUTE			(b3_1)

#define ADC_L1_UNMUTE		(b2_0)
#define ADC_L1_MUTE			(b2_1)

#define ADC_HP_FILT_OFF		(b1_0)
#define ADC_HP_FILT_ON		(b1_1)

#define ADC_PWR_UP			(b0_0)
#define ADC_PWN_DWN			(b0_1)


//ADC_CONTROL_1		0x000f
#define ADC_LTCH_MID		(b7_0)
#define ADC_LTCH_END		(b7_1)

#define ADC_FMT_I2S			(b6_0 | b5_0)
#define ADC_FMT_TDM			(b6_0 | b5_1)
#define ADC_FMT_AUX			(b6_1 | b5_0)

#define ADC_BLK_DLY_1		(b4_0 | b3_0 | b2_0)
#define ADC_BLK_DLY_0		(b4_0 | b3_0 | b2_1)
#define ADC_BLK_DLY_8		(b4_0 | b3_1 | b2_0)
#define ADC_BLK_DLY_12		(b4_0 | b3_1 | b2_1)
#define ADC_BLK_DLY_16		(b4_1 | b3_0 | b2_0)

#define ADC_WIDTH_24		(b1_0 | b0_0)
#define ADC_WIDTH_20		(b1_0 | b0_1)
#define ADC_WIDTH_16		(b1_1 | b0_1)


//ADC_CONTROL_2		0x0010
#define ADC_BCLK_SRC_PIN		(b7_0)
#define ADC_BCLK_SRC_INTERNAL	(b7_1)

#define ADC_BCLK_SLAVE			(b6_0)
#define ADC_BCLK_MASTER			(b6_1)

#define ADC_CHANNELS_2			(b5_0 | b4_0)
#define ADC_CHANNELS_4			(b5_0 | b4_1)
#define ADC_CHANNELS_8			(b5_1 | b4_0)
#define ADC_CHANNELS_16			(b5_1 | b4_1)

#define ADC_LRCLK_SLAVE			(b3_0)
#define ADC_LRCLK_MASTER		(b3_1)

#define ADC_LRCLK_POL_NORM		(b2_0)
#define ADC_LRCLK_POL_INV		(b2_1)

#define ADC_BCLK_POL_NORM		(b1_0)
#define ADC_BCLK_POL_INV		(b1_1)

#define ADC_LRCLK_FMT_50_50		(b0_0)
#define ADC_LRCLK_FMT_PULSE		(b0_1)


//=================================================================================
// ADAV801 CODEC

//Register 0x00/5:4
#define INTCLK2_DIV_1				b5_0	| b4_0
#define INTCLK2_DIV_1_5				b5_0	| b4_1
#define INTCLK2_DIV_2				b5_1	| b4_0
#define INTCLK2_DIV_3				b5_1	| b4_1
//Register 0x00/3:2
#define INTCLK1_DIV_1					b3_0	| b2_0	
#define INTCLK1_DIV_1_5					b3_0	| b2_1	
#define INTCLK1_DIV_2					b3_1	| b2_0	
#define INTCLK1_DIV_3					b3_1	| b2_1	

//Register 0x04
#define PRI_RX_CLK_SRC_SLAVE		b4_0	| b3_0
#define PRI_RX_CLK_SRC_SPDIF_RX_CLK	b4_0	| b3_1
#define PRI_RX_CLK_SRC_INTCLK1		b4_1	| b3_0
#define PRI_RX_CLK_SRC_INTCLK2		b4_1	| b3_1

//Register 0x05
#define SEC_RX_CLK_SRC_SLAVE		b4_0	| b3_0
#define SEC_RX_CLK_SRC_SPDIF_RX_CLK	b4_0	| b3_1
#define SEC_RX_CLK_SRC_INTCLK1		b4_1	| b3_0
#define SEC_RX_CLK_SRC_INTCLK2		b4_1	| b3_1

//Register 0x06
#define PRI_TX_CLK_SRC_SLAVE		b5_0	| b4_0
#define PRI_TX_CLK_SRC_SPDIF_RX_CLK	b5_0	| b4_1
#define PRI_TX_CLK_SRC_INTCLK1		b5_1	| b4_0
#define PRI_TX_CLK_SRC_INTCLK2		b5_1	| b4_1

//Register 0x07
#define SEC_TX_CLK_SRC_SLAVE		b5_0	| b4_0
#define SEC_TX_CLK_SRC_SPDIF_RX_CLK	b5_0	| b4_1
#define SEC_TX_CLK_SRC_INTCLK1		b5_1	| b4_0
#define SEC_TX_CLK_SRC_INTCLK2		b5_1	| b4_1

//Register 0x0C
#define SPDIF_TX_CLK_SRC_INTCLK1		b2_0	| b1_0
#define SPDIF_TX_CLK_SRC_INTCLK2		b2_0	| b1_1
#define SPDIF_TX_CLK_SRC_SPDIF_RX_CLK	b2_1	| b1_0

//Register 0x62
#define PRI_TX_DAT_SRC_ADC			b5_0 	| b4_0	| b3_0
#define PRI_TX_DAT_SRC_SPDIF_RX		b5_0	| b4_0	| b3_1
#define PRI_TX_DAT_SRC_PRI_RX		b5_0	| b4_1	| b3_0
#define PRI_TX_DAT_SRC_SEC_RX		b5_0	| b4_1	| b3_1
#define PRI_TX_DAT_SRC_SRC			b5_1	| b4_0	| b3_0
//Register 0x62
#define SEC_TX_DAT_SRC_ADC			b2_0 	| b1_0	| b0_0
#define SEC_TX_DAT_SRC_SPDIF_RX		b2_0	| b1_0	| b0_1
#define SEC_TX_DAT_SRC_PRI_RX		b2_0	| b1_1	| b0_0
#define SEC_TX_DAT_SRC_SEC_RX		b2_0	| b1_1	| b0_1
#define SEC_TX_DAT_SRC_SRC			b2_1	| b1_0	| b0_0

//Register 0x63
#define SPDIF_TX_DAT_SRC_ADC			b2_0 	| b1_0	| b0_0
#define SPDIF_TX_DAT_SRC_SPDIF			b2_0	| b1_0	| b0_1
#define SPDIF_TX_DAT_SRC_PRI_RX			b2_0	| b1_1	| b0_0
#define SPDIF_TX_DAT_SRC_SEC_RX			b2_0	| b1_1	| b0_1
#define SPDIF_TX_DAT_SRC_SRC			b2_1	| b1_0	| b0_0

//Register 0x74/7:6
#define SCLK3_SRC_PLL2_CLK				b7_0	| b6_0	
#define SCLK3_SRC_SPDIF_RX_CLK			b7_1	| b6_1	
//Register 0x74/0
#define FS3_FS_RATIO_512FS				b0_0
#define FS3_FS_RATIO_256FS				b0_1

//Register 0x75/7:6
#define FS2_FS_SEL_48K					b7_0	| b6_0	
#define FS2_FS_SEL_32K					b7_1	| b6_0	
#define FS2_FS_SEL_441K					b7_1	| b6_1	
//Register 0x75/5
#define FS2_FS_RATIO_256FS				b5_0
#define FS2_FS_RATIO_384FS				b5_1
//Register 0x75/4
#define FS2_MUL_1						b4_0
#define FS2_MUL_2						b4_1
//Register 0x75/3:2
#define FS1_FS_SEL_48K					b3_0	| b2_0	
#define FS1_FS_SEL_32K					b3_1	| b2_0	
#define FS1_FS_SEL_441K					b3_1	| b2_1	
//Register 0x75/1
#define FS1_FS_RATIO_256FS				b1_0
#define FS1_FS_RATIO_384FS				b1_1
//Register 0x75/0
#define FS1_MUL_1						b0_0
#define FS1_MUL_2						b0_1

//Register 0x76/1:0
#define INTCLK2_SRC_XIN					b1_0	| b0_0
#define INTCLK2_SRC_MCLK				b1_0	| b0_1
#define INTCLK2_SRC_PLLINT1				b1_1	| b0_0
#define INTCLK2_SRC_PLLINT2				b1_1	| b0_1

//Register 0x77/4:3
#define INTCLK1_SRC_XIN					b4_0	| b3_0
#define INTCLK1_SRC_MCLK				b4_0	| b3_1
#define INTCLK1_SRC_PLLINT1				b4_1	| b3_0
#define INTCLK1_SRC_PLLINT2				b4_1	| b3_1
//Register 0x77/2:1
#define PLL2_FS2_DIV_1					b2_0 	| b1_0
#define PLL2_FS2_DIV_2					b2_0 	| b1_1
#define PLL2_FS3_DIV_1					b2_1 	| b1_0
#define PLL2_FS3_DIV_2					b2_1 	| b1_1
//Register 0x77/0
#define PLL1_DIV_1						b0_0
#define PLL1_DIV_2						b0_1