segled.rpt

CPLD VHDL 数码管程序

-- Node name is 'seg5' = '~167~1' 
-- Equation name is 'seg5', location is LC011, type is output.
 seg5    = LCELL( _EQ009 $  _EQ010);
  _EQ009 =  dig_reg1 & !dig_reg2 & !dig_reg3 & !dig_reg4 & !dig_reg5 & 
             !dig_reg6 & !_LC127 &  _X004
         # !dig_reg1 &  dig_reg2 & !dig_reg3 & !dig_reg4 & !dig_reg5 & 
             !dig_reg6 & !_LC127 &  _X004
         # !dig_reg1 & !dig_reg2 &  dig_reg3 & !dig_reg4 & !dig_reg5 & 
             !dig_reg6 & !_LC127 &  _X004
         # !dig_reg4 & !dig_reg5 & !dig_reg6 & !_LC127 & !seg5 &  _X004;
  _X004  = EXP( dig_reg3 & !seg5);
  _EQ010 = !_LC127 &  _X004;
  _X004  = EXP( dig_reg3 & !seg5);

-- Node name is 'seg6' = '~166~1' 
-- Equation name is 'seg6', location is LC013, type is output.
 seg6    = LCELL( _EQ011 $  _EQ012);
  _EQ011 = !dig_reg1 & !dig_reg2 & !dig_reg3 & !dig_reg4 &  dig_reg5 & 
             !dig_reg6 & !_LC117 &  _X005 &  _X006
         # !dig_reg1 & !dig_reg2 & !dig_reg3 & !dig_reg4 & !dig_reg5 & 
              dig_reg6 & !_LC117 &  _X005 &  _X006
         # !dig_reg1 & !dig_reg2 & !dig_reg3 & !dig_reg4 & !_LC117 & !seg6 & 
              _X005 &  _X006
         #  dig_reg2 &  dig_reg3 & !_LC117 & !seg6 &  _X005 &  _X006;
  _X005  = EXP( dig_reg5 & !seg6);
  _X006  = EXP( dig_reg6 & !seg6);
  _EQ012 = !_LC117 &  _X005 &  _X006;
  _X005  = EXP( dig_reg5 & !seg6);
  _X006  = EXP( dig_reg6 & !seg6);

-- Node name is 'seg7' = '~165~1' 
-- Equation name is 'seg7', location is LC014, type is output.
 seg7    = LCELL( _EQ013 $  _EQ014);
  _EQ013 =  dig_reg1 & !dig_reg2 & !dig_reg3 & !dig_reg4 & !dig_reg5 & 
             !dig_reg6 & !_LC119 & !_LC124
         # !dig_reg2 & !dig_reg3 & !dig_reg4 & !dig_reg5 & !dig_reg6 & 
             !_LC119 & !_LC124 & !seg7
         #  dig_reg3 &  dig_reg4 & !_LC119 & !_LC124 & !seg7
         #  dig_reg3 &  dig_reg5 & !_LC119 & !_LC124 & !seg7;
  _EQ014 = !_LC119 & !_LC124;

-- Node name is 'seg8' = '~164~1' 
-- Equation name is 'seg8', location is LC016, type is output.
 seg8    = LCELL( _EQ015 $  _EQ016);
  _EQ015 =  dig_reg1 & !dig_reg2 & !dig_reg3 & !dig_reg4 & !dig_reg5 & 
             !dig_reg6 & !_LC107 &  _X007 &  _X008
         # !dig_reg1 & !dig_reg2 & !dig_reg3 &  dig_reg4 & !dig_reg5 & 
             !dig_reg6 & !_LC107 &  _X007 &  _X008
         # !dig_reg2 & !dig_reg3 & !dig_reg5 & !dig_reg6 & !_LC107 & !seg8 & 
              _X007 &  _X008
         #  dig_reg3 &  dig_reg5 & !_LC107 & !seg8 &  _X007 &  _X008;
  _X007  = EXP( dig_reg1 & !seg8);
  _X008  = EXP( dig_reg4 & !seg8);
  _EQ016 = !_LC107 &  _X007 &  _X008;
  _X007  = EXP( dig_reg1 & !seg8);
  _X008  = EXP( dig_reg4 & !seg8);

-- Node name is '~164~2' 
-- Equation name is '~164~2', location is LC107, type is buried.
-- synthesized logic cell 
_LC107   = LCELL( _EQ017 $  GND);
  _EQ017 =  dig_reg3 &  dig_reg6 & !seg8
         #  dig_reg5 &  dig_reg6 & !seg8
         #  dig_reg2 &  dig_reg3 & !seg8
         #  dig_reg2 &  dig_reg5 & !seg8
         #  dig_reg2 &  dig_reg6 & !seg8;

-- Node name is '~165~2' 
-- Equation name is '~165~2', location is LC124, type is buried.
-- synthesized logic cell 
_LC124   = LCELL( _EQ018 $  GND);
  _EQ018 =  dig_reg3 &  dig_reg6 & !seg7
         #  dig_reg4 &  dig_reg5 & !seg7
         #  dig_reg4 &  dig_reg6 & !seg7
         #  dig_reg5 &  dig_reg6 & !seg7
         #  dig_reg2 &  dig_reg3 & !seg7;

-- Node name is '~165~3' 
-- Equation name is '~165~3', location is LC119, type is buried.
-- synthesized logic cell 
_LC119   = LCELL( _EQ019 $  GND);
  _EQ019 =  dig_reg2 &  dig_reg4 & !seg7
         #  dig_reg2 &  dig_reg5 & !seg7
         #  dig_reg2 &  dig_reg6 & !seg7
         #  dig_reg1 & !seg7;

-- Node name is '~166~2' 
-- Equation name is '~166~2', location is LC117, type is buried.
-- synthesized logic cell 
_LC117   = LCELL( _EQ020 $  GND);
  _EQ020 =  dig_reg2 &  dig_reg4 & !seg6
         #  dig_reg3 &  dig_reg4 & !seg6
         #  dig_reg1 &  dig_reg2 & !seg6
         #  dig_reg1 &  dig_reg3 & !seg6
         #  dig_reg1 &  dig_reg4 & !seg6;

-- Node name is '~167~2' 
-- Equation name is '~167~2', location is LC127, type is buried.
-- synthesized logic cell 
_LC127   = LCELL( _EQ021 $  GND);
  _EQ021 =  dig_reg5 &  dig_reg6 & !seg5
         #  dig_reg4 &  dig_reg5 & !seg5
         #  dig_reg4 &  dig_reg6 & !seg5
         #  dig_reg1 & !seg5
         #  dig_reg2 & !seg5;

-- Node name is '~168~2' 
-- Equation name is '~168~2', location is LC115, type is buried.
-- synthesized logic cell 
_LC115   = LCELL( _EQ022 $  GND);
  _EQ022 =  dig_reg2 &  dig_reg6 & !seg4
         # !dig_reg2 & !dig_reg6 & !seg4
         #  dig_reg1 & !seg4
         #  dig_reg3 & !seg4
         #  dig_reg4 & !seg4;

-- Node name is '~169~2' 
-- Equation name is '~169~2', location is LC114, type is buried.
-- synthesized logic cell 
_LC114   = LCELL( _EQ023 $  GND);
  _EQ023 =  dig_reg3 &  dig_reg6 & !seg3
         #  dig_reg4 &  dig_reg5 & !seg3
         #  dig_reg4 &  dig_reg6 & !seg3
         #  dig_reg5 &  dig_reg6 & !seg3
         #  dig_reg1 &  dig_reg3 & !seg3;

-- Node name is '~169~3' 
-- Equation name is '~169~3', location is LC113, type is buried.
-- synthesized logic cell 
_LC113   = LCELL( _EQ024 $  GND);
  _EQ024 =  dig_reg1 &  dig_reg4 & !seg3
         #  dig_reg1 &  dig_reg5 & !seg3
         #  dig_reg1 &  dig_reg6 & !seg3
         #  dig_reg2 & !seg3;

-- Node name is '~170~1~fit~in1' 
-- Equation name is '~170~1~fit~in1', location is LC121, type is buried.
-- synthesized logic cell 
_LC121   = LCELL( _EQ025 $  _EQ026);
  _EQ025 =  dig_reg1 & !dig_reg2 & !dig_reg3 & !dig_reg4 & !dig_reg5 & 
             !dig_reg6 & !_LC122 &  _X009 &  _X010
         # !dig_reg1 & !dig_reg2 & !dig_reg3 &  dig_reg4 & !dig_reg5 & 
             !dig_reg6 & !_LC122 &  _X009 &  _X010
         # !dig_reg2 & !dig_reg3 & !dig_reg5 & !dig_reg6 & !_LC121 & !_LC122 & 
              _X009 &  _X010
         #  dig_reg3 &  dig_reg5 & !_LC121 & !_LC122 &  _X009 &  _X010;
  _X009  = EXP( dig_reg1 & !_LC121);
  _X010  = EXP( dig_reg4 & !_LC121);
  _EQ026 = !_LC122 &  _X009 &  _X010;
  _X009  = EXP( dig_reg1 & !_LC121);
  _X010  = EXP( dig_reg4 & !_LC121);

-- Node name is '~170~2' 
-- Equation name is '~170~2', location is LC122, type is buried.
-- synthesized logic cell 
_LC122   = LCELL( _EQ027 $  GND);
  _EQ027 =  dig_reg3 &  dig_reg6 & !seg2
         #  dig_reg5 &  dig_reg6 & !seg2
         #  dig_reg2 &  dig_reg3 & !seg2
         #  dig_reg2 &  dig_reg5 & !seg2
         #  dig_reg2 &  dig_reg6 & !seg2;

-- Node name is '~171~1' 
-- Equation name is '~171~1', location is LC010, type is buried.
-- synthesized logic cell 
_LC010   = LCELL( _EQ003 $  _EQ004);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                           d:\source\cpld\segled\segled.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,038K