📄 segled.rpt
字号:
- 7 A DFFE + t 0 0 0 0 1 9 12 dig_reg2 (:58)
- 116 H DFFE + t 0 0 0 0 5 9 10 dig_reg1 (:59)
(69) 107 G SOFT s t 1 0 1 0 5 1 0 ~164~2
- 124 H SOFT s t 1 0 1 0 6 1 0 ~165~2
- 119 H SOFT s t 0 0 0 0 6 1 0 ~165~3
(74) 117 H SOFT s t 1 0 1 0 5 1 0 ~166~2
- 127 H SOFT s t 1 0 1 0 6 1 0 ~167~2
(73) 115 H SOFT s t 1 0 1 0 6 1 0 ~168~2
- 114 H SOFT s t 1 0 1 0 6 1 0 ~169~2
- 113 H SOFT s t 0 0 0 0 6 1 0 ~169~3
- 121 H LCELL s t r 3 0 1 0 8 1 1 ~170~1~fit~in1
- 122 H SOFT s t 1 0 1 0 5 0 1 ~170~2
- 10 A LCELL s t 3 2 1 0 7 1 1 ~171~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\source\cpld\segled\segled.rpt
segled
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+--------------------------- LC6 seg1
| +------------------------- LC5 seg2
| | +----------------------- LC3 seg3
| | | +--------------------- LC8 seg4
| | | | +------------------- LC11 seg5
| | | | | +----------------- LC13 seg6
| | | | | | +--------------- LC14 seg7
| | | | | | | +------------- LC16 seg8
| | | | | | | | +----------- LC1 dig_reg6
| | | | | | | | | +--------- LC2 dig_reg5
| | | | | | | | | | +------- LC9 dig_reg4
| | | | | | | | | | | +----- LC4 dig_reg3
| | | | | | | | | | | | +--- LC7 dig_reg2
| | | | | | | | | | | | | +- LC10 ~171~1
| | | | | | | | | | | | | |
| | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'A':
LC3 -> - - * - - - - - - - - - - - | * - - - - - - * | <-- seg3
LC8 -> - - - * - - - - - - - - - - | * - - - - - - * | <-- seg4
LC11 -> - - - - * - - - - - - - - - | * - - - - - - * | <-- seg5
LC13 -> - - - - - * - - - - - - - - | * - - - - - - * | <-- seg6
LC14 -> - - - - - - * - - - - - - - | * - - - - - - * | <-- seg7
LC16 -> - - - - - - - * - - - - - - | * - - - - - * - | <-- seg8
LC1 -> * - * * * * * * - - - - - * | * - - - - - * * | <-- dig_reg6
LC2 -> * - * * * * * * * - - - - * | * - - - - - * * | <-- dig_reg5
LC9 -> * - * * * * * * - * - - - * | * - - - - - - * | <-- dig_reg4
LC4 -> * - * * * * * * - - * - - * | * - - - - - * * | <-- dig_reg3
LC7 -> * - * * * * * * - - - * - * | * - - - - - * * | <-- dig_reg2
LC10 -> * - - - - - - - - - - - - * | * - - - - - - - | <-- ~171~1
Pin
83 -> - - - - - - - - - - - - - - | - - - - - - - - | <-- clk
LC116-> * - * * * * * * - - - - * * | * - - - - - - * | <-- dig_reg1
LC107-> - - - - - - - * - - - - - - | * - - - - - - - | <-- ~164~2
LC124-> - - - - - - * - - - - - - - | * - - - - - - - | <-- ~165~2
LC119-> - - - - - - * - - - - - - - | * - - - - - - - | <-- ~165~3
LC117-> - - - - - * - - - - - - - - | * - - - - - - - | <-- ~166~2
LC127-> - - - - * - - - - - - - - - | * - - - - - - - | <-- ~167~2
LC115-> - - - * - - - - - - - - - - | * - - - - - - - | <-- ~168~2
LC114-> - - * - - - - - - - - - - - | * - - - - - - - | <-- ~169~2
LC113-> - - * - - - - - - - - - - - | * - - - - - - - | <-- ~169~3
LC121-> - * - - - - - - - - - - - - | * - - - - - - * | <-- ~170~1~fit~in1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\source\cpld\segled\segled.rpt
segled
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'G':
Logic cells placed in LAB 'G'
+- LC107 ~164~2
|
| Other LABs fed by signals
| that feed LAB 'G'
LC | | A B C D E F G H | Logic cells that feed LAB 'G':
Pin
83 -> - | - - - - - - - - | <-- clk
LC16 -> * | * - - - - - * - | <-- seg8
LC1 -> * | * - - - - - * * | <-- dig_reg6
LC2 -> * | * - - - - - * * | <-- dig_reg5
LC4 -> * | * - - - - - * * | <-- dig_reg3
LC7 -> * | * - - - - - * * | <-- dig_reg2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\source\cpld\segled\segled.rpt
segled
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+------------------------------- LC118 dig1
| +----------------------------- LC120 dig2
| | +--------------------------- LC123 dig3
| | | +------------------------- LC125 dig4
| | | | +----------------------- LC126 dig5
| | | | | +--------------------- LC128 dig6
| | | | | | +------------------- LC116 dig_reg1
| | | | | | | +----------------- LC124 ~165~2
| | | | | | | | +--------------- LC119 ~165~3
| | | | | | | | | +------------- LC117 ~166~2
| | | | | | | | | | +----------- LC127 ~167~2
| | | | | | | | | | | +--------- LC115 ~168~2
| | | | | | | | | | | | +------- LC114 ~169~2
| | | | | | | | | | | | | +----- LC113 ~169~3
| | | | | | | | | | | | | | +--- LC121 ~170~1~fit~in1
| | | | | | | | | | | | | | | +- LC122 ~170~2
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'H'
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
LC116-> * * - - - - * - * * * * * * * - | * - - - - - - * | <-- dig_reg1
LC121-> - - - - - - - - - - - - - - * - | * - - - - - - * | <-- ~170~1~fit~in1
LC122-> - - - - - - - - - - - - - - * - | - - - - - - - * | <-- ~170~2
Pin
83 -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- clk
LC5 -> - - - - - - - - - - - - - - - * | - - - - - - - * | <-- seg2
LC3 -> - - - - - - - - - - - - * * - - | * - - - - - - * | <-- seg3
LC8 -> - - - - - - - - - - - * - - - - | * - - - - - - * | <-- seg4
LC11 -> - - - - - - - - - - * - - - - - | * - - - - - - * | <-- seg5
LC13 -> - - - - - - - - - * - - - - - - | * - - - - - - * | <-- seg6
LC14 -> - - - - - - - * * - - - - - - - | * - - - - - - * | <-- seg7
LC1 -> - - - - - - - * * - * * * * * * | * - - - - - * * | <-- dig_reg6
LC2 -> * - - - - * * * * - * - * * * * | * - - - - - * * | <-- dig_reg5
LC9 -> * - - - * - * * * * * * * * * - | * - - - - - - * | <-- dig_reg4
LC4 -> * - - * - - * * - * - * * - * * | * - - - - - * * | <-- dig_reg3
LC7 -> * - * - - - * * * * * * - * * * | * - - - - - * * | <-- dig_reg2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\source\cpld\segled\segled.rpt
segled
** EQUATIONS **
clk : INPUT;
-- Node name is ':59' = 'dig_reg1'
-- Equation name is 'dig_reg1', location is LC116, type is buried.
dig_reg1 = DFFE( _EQ001 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !dig_reg1 & !dig_reg2 & !dig_reg3 & !dig_reg4 & !dig_reg5;
-- Node name is ':58' = 'dig_reg2'
-- Equation name is 'dig_reg2', location is LC007, type is buried.
dig_reg2 = DFFE( dig_reg1 $ GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':57' = 'dig_reg3'
-- Equation name is 'dig_reg3', location is LC004, type is buried.
dig_reg3 = DFFE( dig_reg2 $ GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':56' = 'dig_reg4'
-- Equation name is 'dig_reg4', location is LC009, type is buried.
dig_reg4 = DFFE( dig_reg3 $ GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':55' = 'dig_reg5'
-- Equation name is 'dig_reg5', location is LC002, type is buried.
dig_reg5 = DFFE( dig_reg4 $ GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':54' = 'dig_reg6'
-- Equation name is 'dig_reg6', location is LC001, type is buried.
dig_reg6 = DFFE( dig_reg5 $ GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'dig1' = 'dig_regn1'
-- Equation name is 'dig1', location is LC118, type is output.
dig1 = DFFE( _EQ002 $ VCC, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !dig_reg1 & !dig_reg2 & !dig_reg3 & !dig_reg4 & !dig_reg5;
-- Node name is 'dig2' = 'dig_regn2'
-- Equation name is 'dig2', location is LC120, type is output.
dig2 = DFFE( dig_reg1 $ VCC, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'dig3' = 'dig_regn3'
-- Equation name is 'dig3', location is LC123, type is output.
dig3 = DFFE( dig_reg2 $ VCC, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'dig4' = 'dig_regn4'
-- Equation name is 'dig4', location is LC125, type is output.
dig4 = DFFE( dig_reg3 $ VCC, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'dig5' = 'dig_regn5'
-- Equation name is 'dig5', location is LC126, type is output.
dig5 = DFFE( dig_reg4 $ VCC, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'dig6' = 'dig_regn6'
-- Equation name is 'dig6', location is LC128, type is output.
dig6 = DFFE( dig_reg5 $ VCC, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'seg1'
-- Equation name is 'seg1', location is LC006, type is output.
seg1 = LCELL( _EQ003 $ _EQ004);
_EQ003 = !dig_reg1 & !dig_reg2 & !dig_reg3 & !dig_reg4 & !dig_reg5 &
dig_reg6 & _LC010 & _X001 & _X002
# !dig_reg1 & !dig_reg2 & !dig_reg3 & !dig_reg4 & dig_reg5 &
!dig_reg6 & _LC010 & _X001 & _X002
# !dig_reg1 & !dig_reg2 & !dig_reg3 & dig_reg4 & !dig_reg5 &
!dig_reg6 & _LC010 & _X001 & _X002
# !dig_reg1 & !dig_reg2 & dig_reg3 & !dig_reg4 & !dig_reg5 &
!dig_reg6 & _LC010 & _X001 & _X002;
_X001 = EXP( dig_reg1 & !dig_reg2 & !dig_reg3 & !dig_reg4 & !dig_reg5 &
!dig_reg6);
_X002 = EXP(!dig_reg1 & dig_reg2 & !dig_reg3 & !dig_reg4 & !dig_reg5 &
!dig_reg6);
_EQ004 = _LC010 & _X001 & _X002;
_X001 = EXP( dig_reg1 & !dig_reg2 & !dig_reg3 & !dig_reg4 & !dig_reg5 &
!dig_reg6);
_X002 = EXP(!dig_reg1 & dig_reg2 & !dig_reg3 & !dig_reg4 & !dig_reg5 &
!dig_reg6);
-- Node name is 'seg2' = '~170~1'
-- Equation name is 'seg2', location is LC005, type is output.
seg2 = LCELL( _LC121 $ GND);
-- Node name is 'seg3' = '~169~1'
-- Equation name is 'seg3', location is LC003, type is output.
seg3 = LCELL( _EQ005 $ _EQ006);
_EQ005 = !dig_reg1 & dig_reg2 & !dig_reg3 & !dig_reg4 & !dig_reg5 &
!dig_reg6 & !_LC113 & !_LC114
# !dig_reg1 & !dig_reg3 & !dig_reg4 & !dig_reg5 & !dig_reg6 &
!_LC113 & !_LC114 & !seg3
# dig_reg3 & dig_reg4 & !_LC113 & !_LC114 & !seg3
# dig_reg3 & dig_reg5 & !_LC113 & !_LC114 & !seg3;
_EQ006 = !_LC113 & !_LC114;
-- Node name is 'seg4' = '~168~1'
-- Equation name is 'seg4', location is LC008, type is output.
seg4 = LCELL( _EQ007 $ _EQ008);
_EQ007 = dig_reg1 & !dig_reg2 & !dig_reg3 & !dig_reg4 & !dig_reg5 &
!dig_reg6 & !_LC115 & _X003
# !dig_reg1 & !dig_reg2 & dig_reg3 & !dig_reg4 & !dig_reg5 &
!dig_reg6 & !_LC115 & _X003
# !dig_reg1 & !dig_reg2 & !dig_reg3 & dig_reg4 & !dig_reg5 &
!dig_reg6 & !_LC115 & _X003
# !dig_reg1 & !dig_reg2 & !dig_reg3 & !dig_reg4 & dig_reg5 &
!dig_reg6 & !_LC115 & _X003;
_X003 = EXP( dig_reg5 & !seg4);
_EQ008 = !_LC115 & _X003;
_X003 = EXP( dig_reg5 & !seg4);
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